Getting only High Z on output

Question

I am designing a simple bus with 3-state buffers. My buffers work fine, but in my design I only get 8'bZZZZZZZZ output whether the select is 1 or 0. Here is the design that I am working on:

Here is my code:

module part_1(
    input wire select,
    input wire[7:0]data_1,
    input wire[7:0]data_2,
    
    output reg [7:0]out
);
    wire [7:0]out1;
    wire [7:0]out2;

    three_state_buffer TSB1(.enable(~select), .in(data_1), .out(out1));
    three_state_buffer TSB2(.enable(select), .in(data_2), .out(out2));
    
    always@(*) begin
    if(select)
        begin
            out <= out2;
        end
    else
        begin
            out <= out1;
        end
    
    end
endmodule

My three_state_buffer modules returns input if the select is 1 and returns 8-bit high-z if the select is 0.

score 0 · Answer 1 · answered Apr 28 '23 at 14:11

The part_1 module is fine. The problem is either in the three_state_buffer module or your testbench. Here is code that does what you want:

module three_state_buffer (input enable, input [7:0] in, output [7:0] out);
    assign out = (enable) ? in : 'z;
endmodule

module tb;
    bit [7:0] data_1 = 'h33;
    bit [7:0] data_2 = 'hcc;
    bit select;
    wire [7:0] out;

    part_1 dut (
            // Inputs:
        .data_1  (data_1),
        .data_2  (data_2),
        .select  (select),
            // Outputs:
        .out     (out)
    );

    initial begin
        $monitorh(select,,data_1,,data_2,,out);
        #5 select = 1;
        #5 $finish;
    end
endmodule

Output:

0 33 cc 33
1 33 cc cc

Greg · Answer 2 · 2023-04-29T17:18:44.327

For tri-state you do not need to have the always block acting as a mux. As long as there are no conflicting drivers, you can have both three_state_buffer output onto the same net. Simple change the out to a wire type and connect the output. This will also be a closer match to your diagram.

module part_1(
    input wire select,
    input wire[7:0]data_1,
    input wire[7:0]data_2,
    
    output wire [7:0]out
);
    three_state_buffer TSB1(.enable(~select), .in(data_1), .out(out));
    three_state_buffer TSB2(.enable(select), .in(data_2), .out(out));
endmodule

What you had should have worked in simulation. Best guess is the output was not connected properly in the testbench or the enable in the buffer is inverted.

score -1 · Answer 3 · answered Apr 28 '23 at 19:02

Modifying your code just a little bit gets you there.

module part_1(
    input wire select,
    input wire[7:0]data_1,
    input wire[7:0]data_2,
    
    output reg [7:0]out
);
    bit [7:0]out1;  // Usage of two-state type bit results in Z's a 0's
    bit [7:0]out2;

    three_state_buffer TSB1(.enable(~select), .in(data_1), .out(out1));
    three_state_buffer TSB2(.enable(select), .in(data_2), .out(out2));
    
    always@(*) begin
        begin
            out <= out1 | out2; // Bitwise OR of two bit type busses
        end
    end
endmodule

There is no problem with the original `part_1` module. Why do you think your code fixes something in the original code? — toolic, Apr 28 '23 at 19:04

Getting only High Z on output

3 Answers3