PWM only works when I do a reset on dsPIC33EV256GM102

Question

PWM Modul works discontinuously on the DSPIC

Hello everyone,

I am facing a small problem with PWM in my dsPIC33EV256GM102.

I started with a very simple configuration to generate three different duty cycles. Yet the PWM sometimes works sometimes not when I power the circuit. Everytime I do a reset it works but it should not be that way. Decoupling Capacitors are there and the program has just PWM, Timer1 and UART. TImer1 does the only interrupt. Here is my code configuration for PWM and thanks in advance for every help:

    void PWM_Initialize (void)
    {
        // PCLKDIV 1; 
        PTCON2 = 0x00;
        // PTPER 288; 
        PTPER = 0x120;
        // SEVTCMP 0; 
        SEVTCMP = 0x00;
        // MDC 288; 
        MDC = 0x120;
        // CHOPCLK 0; CHPCLKEN disabled; 
        CHOP = 0x00;
        // PWMKEY 0; 
        PWMKEY = 0x00;
        // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time for all Output modes; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; DTCP disabled; 
        PWMCON1 = 0x00;
        // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time for all Output modes; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; DTCP disabled; 
        PWMCON2 = 0x00;
        // MDCS Primary; FLTIEN disabled; CAM Edge Aligned; DTC Positive dead time for all Output modes; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; DTCP disabled; 
        PWMCON3 = 0x00;
        //FLTDAT PWM1L Low, PWM1H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM1L Low, PWM1H Low; OVRDAT PWM1L Low, PWM1H Low; POLH disabled; 
        __builtin_write_PWMSFR(&IOCON1, 0xC000, &PWMKEY);
        //FLTDAT PWM2L Low, PWM2H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM2L Low, PWM2H Low; OVRDAT PWM2L Low, PWM2H Low; POLH disabled; 
        __builtin_write_PWMSFR(&IOCON2, 0xC000, &PWMKEY);
        //FLTDAT PWM3L Low, PWM3H Low; SWAP disabled; OVRENH disabled; PENL enabled; PMOD Complementary Output Mode; OVRENL disabled; OSYNC disabled; POLL disabled; PENH enabled; CLDAT PWM3L Low, PWM3H Low; OVRDAT PWM3L Low, PWM3H Low; POLH disabled; 
        __builtin_write_PWMSFR(&IOCON3, 0xC000, &PWMKEY);
        //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM1H, PWM1L pins to FLTDAT values- Latched; IFLTMOD disabled; FLTSRC FLT32; 
        __builtin_write_PWMSFR(&FCLCON1, 0xF8, &PWMKEY);
        //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM2H, PWM2L pins to FLTDAT values- Latched; IFLTMOD disabled; FLTSRC FLT32; 
        __builtin_write_PWMSFR(&FCLCON2, 0xF8, &PWMKEY);
        //FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD PWM3H, PWM3L pins to FLTDAT values- Latched; IFLTMOD disabled; FLTSRC FLT32; 
        __builtin_write_PWMSFR(&FCLCON3, 0xF8, &PWMKEY);
        // PDC1 256; 
        PDC1 = 0x100;
        // PDC2 96; 
        PDC2 = 0x60;
        // PDC3 32; 
        PDC3 = 0x20;
        // PHASE1 0; 
        PHASE1 = 0x00;
        // PHASE2 0; 
        PHASE2 = 0x00;
        // PHASE3 0; 
        PHASE3 = 0x00;
        // DTR1 0; 
        DTR1 = 0x00;
        // DTR2 0; 
        DTR2 = 0x00;
        // DTR3 0; 
        DTR3 = 0x00;
        // ALTDTR1 0; 
        ALTDTR1 = 0x00;
        // ALTDTR2 0; 
        ALTDTR2 = 0x00;
        // ALTDTR3 0; 
        ALTDTR3 = 0x00;
        // TRGCMP 0; 
        TRIG1 = 0x00;
        // TRGCMP 0; 
        TRIG2 = 0x00;
        // TRGCMP 0; 
        TRIG3 = 0x00;
        // TRGDIV 1; TRGSTRT 0; 
        TRGCON1 = 0x00;
        // TRGDIV 1; TRGSTRT 0; 
        TRGCON2 = 0x00;
        // TRGDIV 1; TRGSTRT 0; 
        TRGCON3 = 0x00;
        // PWMCAP 0; 
        PWMCAP1 = 0x00;
        // PWMCAP 0; 
        PWMCAP2 = 0x00;
        // PWMCAP 0; 
        PWMCAP3 = 0x00;
        // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled; 
        LEBCON1 = 0x00;
        // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled; 
        LEBCON2 = 0x00;
        // BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled; 
        LEBCON3 = 0x00;
        // LEB 0; 
        LEBDLY1 = 0x00;
        // LEB 0; 
        LEBDLY2 = 0x00;
        // LEB 0; 
        LEBDLY3 = 0x00;
        // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking; 
        AUXCON1 = 0x00;
        // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking; 
        AUXCON2 = 0x00;
        // CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking; 
        AUXCON3 = 0x00;
     
     
        // SYNCOEN disabled; SEIEN disabled; SESTAT disabled; SEVTPS 1; SYNCSRC SYNCI1; SYNCEN disabled; PTSIDL disabled; PTEN enabled; EIPU disabled; SYNCPOL disabled; 
        PTCON = 0x8000;
    }