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I am trying to compile a game (program1.exe) and editor(program2.exe) which share many of thesame source files, currently i use a #define in the source files, but i'd like to automate this if its even possible and move this to the makefile.

The text below is a short example of the situation.

Makefile:

all: Program1.exe

CC=gcc
CFLAGS=-Wall

OBJECTS= .obj/main.o .obj/test.o .obj/example.o\


Program1.exe:       $(OBJECTS)
    $(CC) -o "$@" $^

Program2.exe:       $(OBJECTS)
    $(CC) -o "$@" $^
    
    
    
.obj/main.o:            main.c      test.h example.h
$(CC) -c -o $@ $< $(CFLAGS)

.obj/test.o:            test.c          test.h
$(CC) -c -o $@ $< $(CFLAGS)

.obj/example.o: example.c   example.h
$(CC) -c -o $@ $< $(CFLAGS)


two: Program2.exe

Basically running 'make' compiles Program1.exe, while 'make two' will compile Program2.exe I wonna be able to pass a define and only when compiling program2.exe

Expected result is this: When i compile Program1 (make), i want the object files to move to .obj/ (this works) When i compile Program2 (make two) i want the object files to move to subdirectory .obj/editor/ and i need to pass a define -DEDITOR so the source files compile certain parts of the source code.

When i add the following to the makefile:

CFLAGS+= -DEDITOR

It actually works, but it compiles both programs with that flag, which is not what i want.

I also tried making a copy of all the objects with a different subdirectory name:

EOBJECTS= .obj/editor/main.o .obj/editor/test.o .obj/editor/example.c\

.obj/editor/example.c   example.h
$(CC) -c -o $@ $< $(CFLAGS)

Then also adding:

.obj/editor/%.o: CFLAGS += -DEDITOR

Program2.exe:       $(EOBJECTS)
    $(CC) -o "$@" $^

This actually works but messes up my makefile, it has an insane amount of lines and is not very good for upkeeping the file towards the future, since i have each object duplicated.

I also tried a common solution on the internet, but this does not apply the define to my source files for some reason:

Program2.exe:       $(OBJECTS)
    $(CC) -DEDITOR -o "$@" $^

Is there a way to add a define to only one out of multiple make targets and make a copy of the current object files, so i can compile both programs individually who share thesame source?

Askalot
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  • What make flavor are you using? With gnu make you can use target specific variables, and use the private flag to avoid it being shared in unexpected places. You don't explain why this doesn't work for you. Don't repeat your build command but either use an implicit rule, or create a pattern rule. Hard-coding whatever flag is a bad direction (IMHO). This is not a c question, it's a makefile q, btw, so I suggest you remove the c tag. – Allan Wind Mar 25 '23 at 03:35
  • Since they use the same object files, that means you need two copies of the object files, one set compiled for `Program1` and one set compiled for `Program2`. The easiest way to do that is to place the object files in program-specific subdirectories, and use different rules to produce the object files in each subdirectory (e.g. one with the macro definition and one without it). – Tom Karzes Mar 25 '23 at 03:40
  • VPATH, btw, is useful for this. – Allan Wind Mar 25 '23 at 03:41
  • @AllanWind Thanks for the quick reply, i'm using gnu. I have managed to fix the first issue by using a target specific variable as you suggested (i'm a newb with makefiles, so had to look it up). When i tried this before, i added this in the 'program2.exe: ...' part. Now i have i have added this at the bottom, so i have 2x 'two: ...', one to add this define to cflags, and the other to build the exe (assuming this is what you meant). I will check out vpath tomorrow since its 5 :) – Askalot Mar 25 '23 at 04:23

0 Answers0