How not to write "always@(posedge clk) and always@(negedge clk)" in one module

Question

I learn "Do not mix negedge posedge for the same clock in one module (synthesis is possible, but analysis is difficult)"

"So chat gpt

always @(posedge clk)
    ...
always @(negedge clk)

I was wondering how to change this shape.

always @(posedge clk) begin
// Code that executes on the positive edge of the clock
    if (/* condition */) begin
    // Code that executes on the negative edge of the clock
    end
end

It is recommended to change to this form. So, when I changed the code below to the second code, the waveform is different. How do I change it when negedge and posedge are used together in one module?"

first code wave form enter image description here

second code wave form enter image description here

first code

`timescale 1ns / 1ps

module DEFF (
    input clk, reset, in,
    output out
);

    reg trig1 = 0, trig2 = 0;

    assign out = trig1 ^ trig2;

always @(posedge clk, posedge reset) begin
    if (reset) trig1 <= 0;
    trig1 <= in^trig2;
end

always @(negedge clk, posedge reset) begin
    if (reset) trig2 <= 0;
    trig2 <= in^trig1;
end

endmodule

second code

module DEFF (
    input clk, reset, in,
    output out
);

reg clk_prev = 1'b0;
reg trig1 = 0, trig2 = 0;
reg pos_edge_detected = 0;
reg neg_edge_detected = 0;

assign out = trig1 ^ trig2;

always @(posedge clk, posedge reset) begin
    if (reset) begin
        trig1 <= 0;
        trig2 <= 0;
    end else begin
        trig1 <= in ^ trig2;
        if (!trig1) begin
            trig2 <= in ^ trig1;
        end
    end
end
endmodule

testbench

`timescale 1ns / 1ps

module TB_DEFF;

    // Inputs
    reg clk;
    reg reset = 0;
    reg in;
    // Outputs
    wire out;

    // Instantiate the Unit Under Test (UUT)
    DEFF DUT (
        .clk(clk),
        .reset(reset),
        .in(in),
        .out(out)
    );

    always #5 clk = ~clk;

    // Toggle the clock and input
    initial begin
        clk = 0;
        reset = 1;
        in = 0;
        #10 reset = 0;
        #10 in = 1;
        #20 in = 0;
        #20 in = 1;
        #20 in = 0;
        #20 $finish;
    end

endmodule

Why do you want to trigger on both clk edges when you (rightfully so) stated that this is a bad idea? — Max, Mar 21 '23 at 08:02
The current form of chatGPT is not intended to be used to learn Verilog — Greg, Mar 21 '23 at 22:59

score -1 · Answer 1 · answered Mar 21 '23 at 08:01

You do not need to specify an edge in the sensitivity list, this will trigger the always block on any signal level change.

E.g.

always @(posedge clk, rst) 
begin
    if(rst) 
        //reset signals
    else 
        //clocked logic
end

Will create an asynchronous (active high) reset signal. You can also do things like always @(a,b,c) to trigger on any change of a or b or c (see here).

As for you code, your first example (seemingly taken from here) is a double edge triggered FF (as might be inferred by the presence of both posedge and negedge blocks). Your second example is a 'traditional' positive edge triggered FF with a active high synchronous reset. Why would you assume the code produces the same waveform?

Did chatGPT tell you or did you tell it to write it that way? Because the statement // Code that executes on the negative edge of the clock in your second block of code is wrong. That piece of code will execute on every positve clk edge when condition is met!

You need to specify the edge for `rst`. As is a posedge will trigger the reset condition (expected) and a negedge will trigger a else condition regardless the the status of the clock (bad). Use `@(posedge clk, posedge rst)` for a flip-flop with asynchronous active high reset — Greg, Mar 21 '23 at 22:49

How not to write "always@(posedge clk) and always@(negedge clk)" in one module

1 Answers1