output or inout port must be connected to a structural net expression

Question

Block1

module block1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outA = inA;
    outB = outA;
    outC = outB;
end
endmodule

Block2

module block2 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outC = outB;
    outA = inA;
    outB = outA;
end
endmodule

Block3

module block3 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outB = outA;
    outA = inA;
    outC = outB;
end
endmodule

Code the following DUT blocks using 3 different ordering:

module ordering1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
//reg outA, outB, outC;

block1 block1_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block2 block2_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block3 block3_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));

Error:

Error (12014): Net "outA", which fans out to "outA", cannot be assigned more than one value

Error (12015): Net is fed by "block1:block1_inst|outA"

Error (12015): Net is fed by "block2:block2_inst|outA"

Error (12015): Net is fed by "block3:block3_inst|outA"

Error (12014): Net "outB", which fans out to "outB", cannot be assigned more than one value

Error (12015): Net is fed by "block1:block1_inst|outB"

Error (12015): Net is fed by "block2:block2_inst|outB"

Error (12015): Net is fed by "block3:block3_inst|outB"

Error (12014): Net "outC", which fans out to "outC", cannot be assigned more than one value

Error (12015): Net is fed by "block1:block1_inst|outC"

Error (12015): Net is fed by "block2:block2_inst|outC"

Error (12015): Net is fed by "block3:block3_inst|outC"

How to overcome this issue? Thanks.

I have removed reg but the code is still having error after checking the other forum.

Not related to your immediate problem, but you need to use non-blocking assignments. Otherwise there will be a race condition that could result in a mismatch between simulation and synthesis. — Greg, Mar 08 '23 at 17:53

score -1 · Answer 1 · answered Mar 08 '23 at 20:02

Your issue is in the very last statement:

block1 block1_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block2 block2_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block3 block3_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));

In all three instantiations above you drive the same set of signals, outA, outB, and outC three times each by outputs of every instance.

I am not sure which tool generates errors in your case, but in general simulation the error only is generated when out signals are 'reg's. It is ok syntactically if they are nets, as with comment out 'reg' declarations in your example (though it will not work correctly).

anyway, to fix it just instantiate one instance at a time, using generate block or ifdef. Alternatively use different output signals for every different instance, i.e.,

block1 block1_inst (.clk(clk), .inA(inA), .outA(outA1), .outB(outB1), .outC(outC1));
block2 block2_inst (.clk(clk), .inA(inA), .outA(outA2), .outB(outB2), .outC(outC2));
block3 block3_inst (.clk(clk), .inA(inA), .outA(outA3), .outB(outB3), .outC(outC3));

output or inout port must be connected to a structural net expression

1 Answers1