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I am working on an ARMv7 project, which has 2 cores.
According to ARM GICv2 spec. there are 16 PPIs for each core.
So my understanding is the PPI is local to each ARM core, and it should be signaled to and handled by the core.

According to ARM GICv2 spec, the PPI should have the same irq_num for all cores.

I could NOT figure out how is a PPI handled by each core.

Let me use localtimer as an example, each core has an local timer which can interrupt the connected core, in this case, how to install/register the software interrupt handler for that timer interrupt? Or there is a global interrupt handler for the interrupt targets to each core?

wangt13
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1 Answers1

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I found the answer to it.
As GICv2 spec. says, each PPI is private to each Core, and it is not impacted by ITARGETSRn register. Some GIC registers are banked, so each core has its own register to access.

As for the local timer example, each core should configure the same GIC registers to setup the timer interrupt, and the timer interrupt handler can be ran on each core when the PPI is triggered.

This is the local timer interrupt, which can be used as scheduling tick.

wangt13
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