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The question is:

A wide bus configuration has the following parameters:

  • Number of cycles to send the address
  • Number of cycles for a bus transfer = 2 cycles
  • Memory Access = 30 cycles

How many cycles are need to transfer a block of 32 bytes?

So, since it's a wide bus configuration I assumed that the bus transfer cycle will be done over one iteration and same for memory access

Which means that I got 30 + 2 cycles = 32

However I can't make sense of the size of the bus and its impact. I can't understand how i can calculate the the number of cycles left from it

Peter Cordes
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Eimon
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  • You left out some critical details, like the width of the bus (bytes per transfer). I assume it's not 32 bytes wide, but works in burst transfers where you send the address once, and every 2 cycles after that, you get back n bytes of data? Like how an SDRAM burst read or write command works? https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory – Peter Cordes Jan 21 '23 at 21:43
  • Sadly that was all provided in the question There is no missing info – Eimon Jan 21 '23 at 23:50

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