In Verilog how "wire" data type is managed in computer memory?

Question

It's easy to visualize how computer manages to store reg & int variables in memory. Just allocating 1/32 bits respectively in memory and storing the initializing value in binary form. When these variables need to be printed, they are converted back to human readable form, based on the format specifier (%d, %b etc).

**But how computer manages to store wire data type in memory? Since this data type is not meant for storage. ** How computer memory differentiates between data storing variables (int, reg) and data transmission variables (nets).

It would be really helpful, if someone explains in such a way that I can visualize the process going inside computer, while dealing with "wire" data type.

You can not model regs in binary forms because register values can be 0,1,x,z — jsmith, Jan 02 '23 at 12:20

the busybee · Answer 1 · 2023-01-02T14:28:22.470

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This is independent of the hardware description language, it does not matter if this is Verilog or VHDL or any other.

A wire connects "sources" (producers of values on the wire) and "sinks" (consumers of these values). If a wire has no source and no sink, its value cannot be seen, as a "watcher" is a consumer.

One possible implementation for a software object of a wire is a list of producers and consumers.

In case of a simulator: Each time a consumer needs to know the value on the wire, the software object looks up its list of producers and calculates the resulting value.

So your first thought is correct, a software object of a wire commonly does not store the value on the net. But it stores references of other components it connects. By this aspect it is static, as a wire in reality.

edited Jan 02 '23 at 14:28

answered Jan 02 '23 at 12:22

the busybee

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So can we say that "wire" is nothing but a **pointer** to its driver/source? Whenever we access a wire's value, we will be pointed to its driver's value? – Ayush Gemini Jan 03 '23 at 07:40
@AyushGemini This depends on your interpretations of "pointer" and "access". What do _you_ mean? Are we talking about simulation or synthesis? What is your level in programming software? -- Side note: Since a wire can have multiple drivers, its value depends on all of their values. – the busybee Jan 03 '23 at 07:44

score 0 · Answer 2 · answered Jan 06 '23 at 06:35

A wire is not a data type, it represents a network of connections between drivers and receivers, You can say that it is an HDL abstraction for a piece of metal in an electronic circuit. A variable is also an HDL abstraction. It also has the potential to represent a piece of metal, or it could be a register. A register does not store anything; it is an electronic circuit that supplies a current and voltage to a set of transistors connected by wires. It's only when you start talking about non-volatile memory that there begins to be any concept of storage.

How a tool simulating an HDL represents these wires and variables is not directly tied to how they are synthesized into hardware. Technically, a Verilog wire's value is represented by a built-in resolution function of all of its drivers. When any driver changes it's value, the resolution function gets called and computes a resolved value based on the state of the drivers and their strengths. But since the overwhelming majority of wires have only one driver, there's no reason it could not just store the state of the driver in "memory" and use that value whenever some code needs its value.

You might want to read: https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/

In Verilog how "wire" data type is managed in computer memory?

2 Answers2