synchronous Reset doesnt work (VHDL) in Simulation, but why?

Question

I am really confused, because it is a simple code and I dont find the error. Syntax is fine, but in Simulation the Values of Dready and acc_value dont change.

This is my module MVM.vhd:

entity MVM is
  port (
    CLK:        IN  std_logic;
    RST:        IN  std_logic;
    DREADY:     OUT std_logic
  );
end entity MVM;

architecture base of MVM is
begin
  process(CLK)
  variable acc_value : signed(15 downto 0);
  begin
   IF rising_edge(CLK) then   
      IF RST='1' THEN
        acc_value := (OTHERS => '0'); -- reset 
        DREADY <= '0';
      END IF;
    END IF;
  END process;
end base;

If Reset is high, it should set the values of Dready and acc_value to "0"

My Testbench:

entity tb_MVM is
--  Port ( );
end tb_MVM;

architecture TEST of tb_MVM is

  Component MVM
  port (
    CLK:        IN  std_logic;
    RST:        IN  std_logic;
    DREADY:     OUT std_logic
  );
    End component;
    
    signal CLK:        std_logic;
    signal RST:        std_logic;
    signal DREADY:     std_logic;

    BEGIN
          uut:  MVM Port Map(
                CLK=>CLK,
                RST=>RST,
                DREADY => DREADY
                );
           
        tb: process    
        BEGIN
            wait for 100ns;
            CLK <= '1';
            RST <= '1';
            wait for 100ns;
            CLK <= '0';
            wait for 100ns;
            CLK <= '1';
            RST <= '0';
        END PROCESS;   
end TEST;

In the Simulation, the DREADY and acc_value are undefined ('X')

the busybee · Accepted Answer · 2022-12-09T09:13:03.950

2

Assuming you mean the output before 300ns...

In simplified words: rising_edge() checks a transition from '0' to '1', and is not true for transitions from 'X' to '1'.

You might also want to make sure that RST is stable when CLK actually rises, for example:

        tb: process    
        BEGIN
            CLK <= '0';
            RST <= '1';
            wait for 100ns;
            CLK <= '1';
            wait for 100ns;
            CLK <= '0';
            RST <= '0';
        END PROCESS;

This brings DREADY and acc_value to zero after 100ns.

edited Dec 09 '22 at 09:13

answered Dec 08 '22 at 14:58

the busybee

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1

We call those typographical errors or colloquially think-o's where you meant one thing and wrote another. – user16145658 Dec 08 '22 at 15:55
You are right, it should set it to "0" and not to "1". Anyhow, in simulation but it is neither 0 or 1, its "x" (undefined/unknown) – hajo Dec 09 '22 at 08:41

synchronous Reset doesnt work (VHDL) in Simulation, but why?

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