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I know that the ARM 32-bit (AArch32) architecture supports 2 types of page tables: the short format (which has 32-bit table entries) and the long format (which has 64-bit table entries and is known as LPAE).

For the short format, they managed to support a 40-bit address space by allowing the descriptor for 16MB supersections to contain bits 32-39 of the physical address (similar to how x86 does it using PSE-36, but with 4MB pages instead).

However, what I don't understand is why isn't the full 48-bit address space supported when using the long descriptor format. It has the necessary space for the extra bits and they are supported in AArch64, but in AArch32 mode the manual says (G5.5.2):

In both cases, if bits[47:40] of the descriptor are not zero then a translation that uses the descriptor will generate an Address size fault, see Address size fault on page G5-9240.

What is the reason for not supporting the full 48-bit address space? Would it have used so much more silicon, considering that (almost) the same translation scheme is used in both LPAE and A64?

DarkAtom
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  • what did arm say when you asked? – old_timer Dec 02 '22 at 00:09
  • According to the white paper "Principles of ARM Memory Maps" [DEN0001C_principles_of_arm_memory_maps-3.pdf](https://documentation-service.arm.com/static/5ed11654ca06a95ce53f8f0f) from 2012 there were additional proposed 44- and 48-bit Address Maps. Thou since they were only *proposed*, I assume they were never implemented. E.g. Linux only ever introduced [40-bit LPAE](https://lwn.net/Articles/415190/). – luttztfz Aug 15 '23 at 16:36

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