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void SPI_SendData(SPI_RegDef_t *pSPIx ,uint8_t *pTxBuffer,uint32_t len)
{
    while(len > 0)
    {
        // 1. chờ cờ TXE set (chờ cho thanh txbuffer trống)
        while (SPI_GetFlagStatus(pSPIx, SPI_FLAG_TXE) == FLAG_RESET);
        //2. kiểm tra DFF

        if(((pSPIx->CR1 >> SPI_CR1_DFF) & 1) == SPI_DFF_16BIT)
        {
            // 16 bit
            pSPIx->DR = *((uint16_t*) pTxBuffer);
            (uint16_t*) pTxBuffer++;
            len--;

        }else
        {
            pSPIx->DR = *pTxBuffer;
            pTxBuffer++;
        }

         len--;
    }
}

I think, Clearing the TXE bit is performed by writing to the SPI_DR register. The TXE Flag is not cleared but the RXEN flag is turned on when I write data to the SPI_DR register. Why is the RXEN flag is turned on? why is the TXE Flag not cleared?

metisai02
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1 Answers1

0

(uint16_t*) pTxBuffer++; this is wrong

pSPIx->DR = *pTxBuffer; it is wrong as well as it transfers 32 bits instead of 8. If your micro has SPI FIFO - you will send 4 bytes.

Clearing the TXE bit is performed by writing to the SPI_DR register

Yes but when data was moved to the shift register this flag is set indicating that you can put more data. So it will be cleared for a very short time.

Why is the RXEN flag is turned on?

You probably mean RXNE. It is set as master received data at the same time when it transmits (BTW it is the only way to receive anything - you need to transmit dummy data). It is 100% correct behaviour

0___________
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  • Thanks, Sir, but I didn't use any Slave to communicate ( just use the MOSI line ), how can Master receive data? I can see turned on or cleared RXNE flag but I can't see this with TXE (Debugging step by step) – metisai02 Nov 07 '22 at 13:00
  • It does not matter. You always receive when you transmit – 0___________ Nov 07 '22 at 14:08