0

I'm getting a hold time violation from CyBUS_CLK to SineDAC:Wave1_DMA/termout and I'm not quite sure why. I've got two waveforms in a single DAC. Sample rate is 128kSPS, samples for both are 128. Master, bus, and ilo clocks are unspecified. The static timing analysis shows:

CyBYS_CLK --> \SineDAC:Wave1_DMA\/termout : Positive edge
\Phase:Sync:ctrl_reg\/control_0 --> Net_2/main_0  Slack -15.298ns 

CyBYS_CLK --> \SineDAC:Wave2_DMA\/termout : Positive edge
\Phase:Sync:ctrl_reg\/control_0 --> Net_2/main_0  Slack -15.776ns
Trevor
  • 1,369
  • 2
  • 13
  • 28

0 Answers0