How do you escape % in SystemVerilog?

Question

How do you escape % in the SystemVerilog $display statement?

Answer 1

From IEEE Std 1800-2017, section 21.2.1 The display and write tasks:

The special character string %% indicates the display of the percent sign character %

module tb;
    initial $display("hello %% world");
endmodule

The above displays:

hello % world

Run it on EDA playground.

For a more complex example, see How can I automatically scale a $display column width?