0

I have basic query regarding ARM SMMU, as per following link:

https://www.intel.com/content/www/us/en/docs/programmable/683567/21-3/stream-id-falconmesa-stratix-10.html

"Each transaction is also classified by a 10-bit stream ID. The stream ID represents a set or stream of transactions from a particular master device."

What exactly this transaction mean from master device that gets an ID, are these DRAM RAM addresses that master device want to access using DMA via SMMU ?

Milan
  • 1,447
  • 5
  • 19
  • 27

0 Answers0