I'm writing a Makefile for my project. The project is something like this:
config.mk - variables like CC, CFLAGS, PREFIX, etc.
obj
src
|--- include
|--- foo1
| |--- 1.c
| |--- 2.c
| L--- unwanted1.c
L--- foo2
|--- bar1
| |---3.c
| |---4.c
| |---unwanted2.c
| L---unwanted3.c
|--- bar2
|---5.c
L---6.c
I wanted to exclude the unwanted .c files (they were used in a different part of the build process), build them then put the created object files in obj. But I don't know how to build them yet. This is what I've been able to write (and worked):
# Compiler setting are defined here:
include config.mk
SRCS = src/foo1/1.c src/foo1/2.c \
src/foo2/bar1/3.c src/foo2/bar1/4.c \
src/foo2/bar2/5.c src/foo2/bar2/5.c
OBJS = $(addprefix obj/,$(notdir $(SRCS:.c=.o)))
But I don't know how to write the building part. Answers I've found used %.c and %.o, which is impossible in this case. I tried writing it like this:
$(OBJS): $(SRCS)
${CC} -fPIC -c -Isrc/include ${CFLAGS} -o $@ $<
lib: $(OBJS)
${CC} -shared -o lib.so -Wl,-soname="lib.so" $(OBJS)
But it didn't work.
make: *** No rule to make target 'obj/bar1.o', needed by 'lib'. Stop.
How can I rewrite the building part to make it work?
Thanks in advance.