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I'm migrating from Ride7 to Eclipse CDT with GNU arm-none-eabi toolchain.

In my project, I have a hardware register description library using .equ directive in a way like:

.equ BIT_31, 1 << 31
.equ BIT_30, 1 << 30
and so on up to
.equ BIT_0,  1 << 0

I want to prepare a mask to clear e.g. bits 30, 27, 25 and 5.
In Ride7 there was no problem to use pseudo-instruction

ldr r0, =~(BIT_30 | BIT_27 | BIT_25 | BIT_5)

This generated a constant somewhere in a pool and produced LDR r0, [pc, #IMM], or MOV/MVN instruction if nice constant.

But GNU toolchain refuses to evaluate the constant expression producing Syntax error. (I can use only ldr r0, =BIT_30 for example).

Can anyone advise me how to solve this?

Added later:

There are several file sin the project, included in the main one. Here are minimized listings:

main.S:

.syntax unified
.text

.include "defs_swintf.inc"             @ software interface
.include "defs_md.inc"                 @ hardware interface

/***
* Startup
***/
_start:
    .include "startup.S"

/***
* Core
***/

/***
* removed to minimalize
***/
    
/***
* CPU Init
***/
.align 4
Init_CPU: 
    ldr r0, =Init_stack
    mov sp, r0
    bl Set_RESULT_WAIT
    bl Configure_clocks
    ldr r1, =RESULT_OK
    bkpt                                @ halt
    
    .include "procedures.S"
    
.end

startup.S:

.syntax unified
.text

    .word Init_stack                        @ stack pointer
    .word Reset_handler+1                   @ Reset
    .word Default_handler+1                 @ NMI
    .word Default_handler+1                 @ Hardfault
    
Reset_handler:
    b Init_CPU

Default_handler:
    bl Set_RESULT_ERROR
    bkpt                                    @ halt

procedures.S

.syntax unified
.text

/*******************************************************************************
* Configure_clocks
*******************************************************************************/
Configure_clocks:
    push {LR}

        ldr r0, =RCC_CR
        ldr r1, [r0]
        ldr r2, =RCC_CR_HSION_mask
        orr r1, r1, r2
        str r1, [r0]
        ldr r3, =RCC_CFGR
        ldr r4, [r3]
        ldr r2, = ~(RCC_CFGR_HPRE_mask | RCC_CFGR_PPRE1_mask | RCC_CFGR_PPRE2_mask | RCC_CFGR_ADCPRE_mask | RCC_CFGR_MCO_mask)
        and r4, r4, r2
        str r4, [r3]
        ldr r2, = ~RCC_CR_CSSON_mask
        and r1, r1, r2
        str r1, [r0]
        ldr r5, =RCC_CIR
        ldr r2, =RCC_CIR_clearAll
        str r2, [r5]
        ldr r2, =RCC_CR_HSIRDY_mask

    pop {pc}

defs_swintf.inc

/***
* operation results
***/

.equ    RESULT_OK,     0x89abcdef
.equ    RESULT_BAD,    0x4321fedc
.equ    RESULT_WAIT,   0x12345678
.equ    RESULT_ERROR,  0x9876dcba

defs_md.inc

    .equ Init_stack, 0x20005000         /* initial stack */

/***
* device registers
***/

/******************************************************************************/
/* Reequ and Clock Control Registers                                          */
/******************************************************************************/
    .equ RCC_base, 0x40021000
    .equ RCC_CR, RCC_base + 0x00        /* Clock control register             */
    .equ RCC_CR_reequ, 0x00000083
        .equ RCC_CR_HSION_mask,         0x01 << 0
        .equ RCC_CR_HSIRDY_mask,        0x01 << 1
        .equ RCC_CR_HSITRIM_mask,       0x1f << 3
        .equ RCC_CR_HSICAL_mask,        0xff << 8
        .equ RCC_CR_HSEON_mask,         0x01 << 16
        .equ RCC_CR_HSERDY_mask,        0x01 << 17
        .equ RCC_CR_HSEBYP_mask,        0x01 << 18
        .equ RCC_CR_CSSON_mask,         0x01 << 19
        .equ RCC_CR_PLLON_mask,         0x01 << 24
        .equ RCC_CR_PLLRDY_mask,        0x01 << 25
    
    .equ RCC_CFGR, RCC_base + 0x04      /* Clock configuration register       */
    .equ RCC_CFGR_reequ, 0x00000000
        .equ RCC_CFGR_SW_mask,          0x03 << 0
        .equ RCC_CFGR_SW_hsi,           0x00 << 0
        .equ RCC_CFGR_SW_hse,           0x01 << 0
        .equ RCC_CFGR_SW_pll,           0x02 << 0
        
        .equ RCC_CFGR_SWS_mask,         0x03 << 2
        .equ RCC_CFGR_SWS_hsi,          0x00 << 2
        .equ RCC_CFGR_SWS_hse,          0x01 << 2
        .equ RCC_CFGR_SWS_pll,          0x02 << 2
        
        .equ RCC_CFGR_HPRE_mask,        0x0f << 4
        .equ RCC_CFGR_HPRE_div1,        0x00 << 4
        .equ RCC_CFGR_HPRE_div2,        0x08 << 4
        .equ RCC_CFGR_HPRE_div4,        0x09 << 4
        .equ RCC_CFGR_HPRE_div8,        0x0a << 4
        .equ RCC_CFGR_HPRE_div16,       0x0b << 4
        .equ RCC_CFGR_HPRE_div64,       0x0c << 4
        .equ RCC_CFGR_HPRE_div128,      0x0d << 4
        .equ RCC_CFGR_HPRE_div256,      0x0e << 4
        .equ RCC_CFGR_HPRE_div512,      0x0f << 4
        
        .equ RCC_CFGR_PPRE1_mask,       0x07 << 8
        .equ RCC_CFGR_PPRE1_div1,       0x00 << 8
        .equ RCC_CFGR_PPRE1_div2,       0x04 << 8
        .equ RCC_CFGR_PPRE1_div4,       0x05 << 8
        .equ RCC_CFGR_PPRE1_div8,       0x06 << 8
        .equ RCC_CFGR_PPRE1_div16,      0x07 << 8
        
        .equ RCC_CFGR_PPRE2_mask,       0x07 << 11
        .equ RCC_CFGR_PPRE2_div1,       0x00 << 11
        .equ RCC_CFGR_PPRE2_div2,       0x04 << 11
        .equ RCC_CFGR_PPRE2_div4,       0x05 << 11
        .equ RCC_CFGR_PPRE2_div8,       0x06 << 11
        .equ RCC_CFGR_PPRE2_div16,      0x07 << 11
        
        .equ RCC_CFGR_ADCPRE_mask,      0x03 << 14
        .equ RCC_CFGR_ADCPRE_div2,      0x00 << 14
        .equ RCC_CFGR_ADCPRE_div4,      0x01 << 14
        .equ RCC_CFGR_ADCPRE_div6,      0x02 << 14
        .equ RCC_CFGR_ADCPRE_div8,      0x03 << 14
        
        .equ RCC_CFGR_PLLSRC_mask,      0x01 << 16
        .equ RCC_CFGR_PLLSRC_hsiDiv2,   0x00 << 16
        .equ RCC_CFGR_PLLSRC_hse,       0x01 << 16
        
        .equ RCC_CFGR_PLLXTPRE_mask,    0x01 << 17
        .equ RCC_CFGR_PLLXTPRE_hse,     0x00 << 17
        .equ RCC_CFGR_PLLXTPRE_hseDiv2, 0x01 << 17
        
        .equ RCC_CFGR_PLLMUL_mask,      0x0f << 18
        .equ RCC_CFGR_PLLMUL_x2,        0x00 << 18
        .equ RCC_CFGR_PLLMUL_x3,        0x01 << 18
        .equ RCC_CFGR_PLLMUL_x4,        0x02 << 18
        .equ RCC_CFGR_PLLMUL_x5,        0x03 << 18
        .equ RCC_CFGR_PLLMUL_x6,        0x04 << 18
        .equ RCC_CFGR_PLLMUL_x7,        0x05 << 18
        .equ RCC_CFGR_PLLMUL_x8,        0x06 << 18
        .equ RCC_CFGR_PLLMUL_x9,        0x07 << 18
        .equ RCC_CFGR_PLLMUL_x10,       0x08 << 18
        .equ RCC_CFGR_PLLMUL_x11,       0x09 << 18
        .equ RCC_CFGR_PLLMUL_x12,       0x0a << 18
        .equ RCC_CFGR_PLLMUL_x13,       0x0b << 18
        .equ RCC_CFGR_PLLMUL_x14,       0x0c << 18
        .equ RCC_CFGR_PLLMUL_x15,       0x0d << 18
        .equ RCC_CFGR_PLLMUL_x16,       0x0e << 18
        
        .equ RCC_CFGR_USBPRE_mask,      0x01 << 22
        .equ RCC_CFGR_USBPRE_div1_5,    0x00 << 22
        .equ RCC_CFGR_USBPRE_div1,      0x01 << 22
        
        .equ RCC_CFGR_MCO_mask,         0x07 << 24
        .equ RCC_CFGR_MCO_off,          0x00 << 24
        .equ RCC_CFGR_MCO_sysclk,       0x04 << 24
        .equ RCC_CFGR_MCO_hsi,          0x05 << 24
        .equ RCC_CFGR_MCO_hse,          0x06 << 24
        .equ RCC_CFGR_MCO_pllDiv2,      0x07 << 24
    
    .equ RCC_CIR, RCC_base + 0x08       /* Clock interrupt register           */
    .equ RCC_CIR_reequ, 0x00000000
    .equ RCC_CIR_clearAll, 0x009f0000
        .equ RCC_CIR_LSIRDYF_mask,      0x01 << 0
        .equ RCC_CIR_LSERDYF_mask,      0x01 << 1
        .equ RCC_CIR_HSIRDYF_mask,      0x01 << 2
        .equ RCC_CIR_HSERDYF_mask,      0x01 << 3
        .equ RCC_CIR_PLLRDYF_mask,      0x01 << 4
        .equ RCC_CIR_CSSF_mask,         0x01 << 7
        .equ RCC_CIR_LSIRDYIE_mask,     0x01 << 8
        .equ RCC_CIR_LSERDYIE_mask,     0x01 << 9
        .equ RCC_CIR_HSIRDYIE_mask,     0x01 << 10
        .equ RCC_CIR_HSERDYIE_mask,     0x01 << 11
        .equ RCC_CIR_PLLRDYIE_mask,     0x01 << 12
        .equ RCC_CIR_LSIRDYC_mask,      0x01 << 16
        .equ RCC_CIR_LSERDYC_mask,      0x01 << 17
        .equ RCC_CIR_HSIRDYC_mask,      0x01 << 18
        .equ RCC_CIR_HSERDYC_mask,      0x01 << 19
        .equ RCC_CIR_PLLRDYC_mask,      0x01 << 20
        .equ RCC_CIR_CSSC_mask,         0x01 << 23
    
    .equ RCC_APB2RSTR, RCC_base + 0x0c  /* APB2 peripheral reequ register     */
    .equ RCC_APB2RSTR_reequ, 0x00000000
        .equ RCC_APB2RSTR_AFIORST_mask,     0x01 << 0
        .equ RCC_APB2RSTR_IOPARST_mask,     0x01 << 2
        .equ RCC_APB2RSTR_IOPBRST_mask,     0x01 << 3
        .equ RCC_APB2RSTR_IOPCRST_mask,     0x01 << 4
        .equ RCC_APB2RSTR_IOPDRST_mask,     0x01 << 5
        .equ RCC_APB2RSTR_IOPERST_mask,     0x01 << 6
        .equ RCC_APB2RSTR_IOPFRST_mask,     0x01 << 7
        .equ RCC_APB2RSTR_IOPGRST_mask,     0x01 << 8
        .equ RCC_APB2RSTR_ADC1RST_mask,     0x01 << 9
        .equ RCC_APB2RSTR_ADC2RST_mask,     0x01 << 10
        .equ RCC_APB2RSTR_TIM1RST_mask,     0x01 << 11
        .equ RCC_APB2RSTR_SPI1RST_mask,     0x01 << 12
        .equ RCC_APB2RSTR_TIM8RST_mask,     0x01 << 13
        .equ RCC_APB2RSTR_USART1RST_mask,   0x01 << 14
        .equ RCC_APB2RSTR_ADC3RST_mask,     0x01 << 15
        .equ RCC_APB2RSTR_TIM9RST_mask,     0x01 << 19
        .equ RCC_APB2RSTR_TIM10RST_mask,    0x01 << 20
        .equ RCC_APB2RSTR_TIM11RST_mask,    0x01 << 21
    
    .equ RCC_APB1RSTR, RCC_base + 0x10  /* APB1 peripheral reequ register     */
    .equ RCC_APB1RSTR_reequ, 0x00000000
      .equ RCC_APB1RSTR_TIM2RST_mask,       0x01 << 0
      .equ RCC_APB1RSTR_TIM3RST_mask,       0x01 << 1
      .equ RCC_APB1RSTR_TIM4RST_mask,       0x01 << 2
      .equ RCC_APB1RSTR_TIM5RST_mask,       0x01 << 3
      .equ RCC_APB1RSTR_TIM6RST_mask,       0x01 << 4
      .equ RCC_APB1RSTR_TIM7RST_mask,       0x01 << 5
      .equ RCC_APB1RSTR_TIM12RST_mask,      0x01 << 6
      .equ RCC_APB1RSTR_TIM13RST_mask,      0x01 << 7
      .equ RCC_APB1RSTR_TIM14RST_mask,      0x01 << 8
      .equ RCC_APB1RSTR_WWDGRST_mask,       0x01 << 11
      .equ RCC_APB1RSTR_SPI2RST_mask,       0x01 << 14
      .equ RCC_APB1RSTR_SPI3RST_mask,       0x01 << 15
      .equ RCC_APB1RSTR_USART2RST_mask,     0x01 << 17
      .equ RCC_APB1RSTR_USART3RST_mask,     0x01 << 18
      .equ RCC_APB1RSTR_USART4RST_mask,     0x01 << 19
      .equ RCC_APB1RSTR_USART5RST_mask,     0x01 << 20
      .equ RCC_APB1RSTR_I2C1RST_mask,       0x01 << 21
      .equ RCC_APB1RSTR_I2C2RST_mask,       0x01 << 22
      .equ RCC_APB1RSTR_USBRST_mask,        0x01 << 23
      .equ RCC_APB1RSTR_CANRST_mask,        0x01 << 25
      .equ RCC_APB1RSTR_BKPRST_mask,        0x01 << 27
      .equ RCC_APB1RSTR_PWRRST_mask,        0x01 << 28
      .equ RCC_APB1RSTR_DACRST_mask,        0x01 << 29
    
    .equ RCC_AHBENR, RCC_base + 0x14    /* AHB peripheral clock enable rgr.   */
    .equ RCC_AHBENR_reequ, 0x00000014
        .equ RCC_AHBENR_DMA1EN_mask,        0x01 << 0
        .equ RCC_AHBENR_DMA2EN_mask,        0x01 << 1
        .equ RCC_AHBENR_SRAMEN_mask,        0x01 << 2
        .equ RCC_AHBENR_FLITFEN_mask,       0x01 << 4
        .equ RCC_AHBENR_CRCEN_mask,         0x01 << 6
        .equ RCC_AHBENR_FSMCEN_mask,        0x01 << 8
        .equ RCC_AHBENR_SDIOEN_mask,        0x01 << 10
    
    .equ RCC_APB2ENR, RCC_base + 0x18   /* APB2 peripheral clock enable rgr.  */
    .equ RCC_APB2ENR_reequ, 0x00000000
        .equ RCC_APB2ENR_AFIOEN_mask,       0x01 << 0
        .equ RCC_APB2ENR_IOPAEN_mask,       0x01 << 2
        .equ RCC_APB2ENR_IOPBEN_mask,       0x01 << 3
        .equ RCC_APB2ENR_IOPCEN_mask,       0x01 << 4
        .equ RCC_APB2ENR_IOPDEN_mask,       0x01 << 5
        .equ RCC_APB2ENR_IOPEEN_mask,       0x01 << 6
        .equ RCC_APB2ENR_IOPFEN_mask,       0x01 << 7
        .equ RCC_APB2ENR_IOPGEN_mask,       0x01 << 8
        .equ RCC_APB2ENR_ADC1EN_mask,       0x01 << 9
        .equ RCC_APB2ENR_ADC2EN_mask,       0x01 << 10
        .equ RCC_APB2ENR_TIM1EN_mask,       0x01 << 11
        .equ RCC_APB2ENR_SPI1EN_mask,       0x01 << 12
        .equ RCC_APB2ENR_TIM8EN_mask,       0x01 << 13
        .equ RCC_APB2ENR_USART1EN_mask,     0x01 << 14
        .equ RCC_APB2ENR_ADC3EN_mask,       0x01 << 15
        .equ RCC_APB2ENR_TIM9EN_mask,       0x01 << 19
        .equ RCC_APB2ENR_TIM10EN_mask,      0x01 << 20
        .equ RCC_APB2ENR_TIM11EN_mask,      0x01 << 21
    
    .equ RCC_APB1ENR, RCC_base + 0x1c   /* APB1 peripheral clock enable rgr.  */
    .equ RCC_APB1ENR_reequ, 0x00000000
        .equ RCC_APB1ENR_TIM2EN_mask,       0x01 << 0
        .equ RCC_APB1ENR_TIM3EN_mask,       0x01 << 1
        .equ RCC_APB1ENR_TIM4EN_mask,       0x01 << 2
        .equ RCC_APB1ENR_TIM5EN_mask,       0x01 << 3
        .equ RCC_APB1ENR_TIM6EN_mask,       0x01 << 4
        .equ RCC_APB1ENR_TIM7EN_mask,       0x01 << 5
        .equ RCC_APB1ENR_TIM12EN_mask,      0x01 << 6
        .equ RCC_APB1ENR_TIM13EN_mask,      0x01 << 7
        .equ RCC_APB1ENR_TIM14EN_mask,      0x01 << 8
        .equ RCC_APB1ENR_WWDGEN_mask,       0x01 << 11
        .equ RCC_APB1ENR_SPI2EN_mask,       0x01 << 14
        .equ RCC_APB1ENR_SPI3EN_mask,       0x01 << 15
        .equ RCC_APB1ENR_USART2EN_mask,     0x01 << 17
        .equ RCC_APB1ENR_USART3EN_mask,     0x01 << 18
        .equ RCC_APB1ENR_USART4EN_mask,     0x01 << 19
        .equ RCC_APB1ENR_USART5EN_mask,     0x01 << 20
        .equ RCC_APB1ENR_I2C1EN_mask,       0x01 << 21
        .equ RCC_APB1ENR_I2C2EN_mask,       0x01 << 22
        .equ RCC_APB1ENR_USBEN_mask,        0x01 << 23
        .equ RCC_APB1ENR_CANEN_mask,        0x01 << 25
        .equ RCC_APB1ENR_BKPEN_mask,        0x01 << 27
        .equ RCC_APB1ENR_PWREN_mask,        0x01 << 28
        .equ RCC_APB1ENR_DACEN_mask,        0x01 << 29
    
    .equ RCC_BDCR, RCC_base + 0x20      /* Backup domain control register     */
    .equ RCC_BDCR_reequ, 0x00000000
      .equ RCC_BDCR_LSEON_mask,             0x01 << 0
      .equ RCC_BDCR_LSERDY_mask,            0x01 << 1
      .equ RCC_BDCR_LSEBYP_mask,            0x01 << 2
      
      .equ RCC_BDCR_RTCSEL_mask,            0x03 << 8
      .equ RCC_BDCR_RTCSEL_noClock,         0x00
      .equ RCC_BDCR_RTCSEL_lse,             0x01 << 8
      .equ RCC_BDCR_RTCSEL_lsi,             0x02 << 8
      .equ RCC_BDCR_RTCSEL_hse,             0x03 << 8
      
      .equ RCC_BDCR_RTCEN_mask,             0x01 << 15
      .equ RCC_BDCR_BDRST_mask,             0x01 << 16
    
    .equ RCC_CSR, RCC_base + 0x24       /* Control/status register            */
    .equ RCC_CSR_reequ, 0x0C000000
        .equ RCC_CSR_LSION_mask,            0x01 << 0
        .equ RCC_CSR_LSIRDY_mask,           0x01 << 1
        .equ RCC_CSR_RMVF_mask,             0x01 << 24
        .equ RCC_CSR_PINRSTF_mask,          0x01 << 26
        .equ RCC_CSR_PORRSTF_mask,          0x01 << 27
        .equ RCC_CSR_SFTRSTF_mask,          0x01 << 28
        .equ RCC_CSR_IWDGRSTF_mask,         0x01 << 29
        .equ RCC_CSR_WWDGRSTF_mask,         0x01 << 30
        .equ RCC_CSR_LPWRRSTF_mask,         0x01 << 31

Finally, the console output:

11:43:02 **** Incremental Build of configuration Debug for project minimal ****
make all 
Building file: ../src/main.S
Invoking: GNU Arm Cross Assembler
arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections  -g3 -x assembler-with-cpp -I"E:\_ARM_workspace2\minimal\src" -I"E:\_ARM_workspace2\minimal\inc" -Wa,-adhlns="src/main.o.lst" --save-temps -v -MMD -MP -MF"src/main.d" -MT"src/main.o" -c -o "src/main.o" "../src/main.S"
Using built-in specs.
COLLECT_AS_OPTIONS='-adhlns=src/main.o.lst'
COLLECT_GCC=arm-none-eabi-gcc
Target: arm-none-eabi
Configured with: /Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/sources/gcc/configure --prefix=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc --prefix=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc --infodir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/info --mandir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/man --htmldir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/html --pdfdir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/pdf --build=x86_64-pc-linux-gnu --host=x86_64-w64-mingw32 --target=arm-none-eabi --disable-libgomp --disable-libmudflap --disable-libquadmath --disable-libsanitizer --disable-libssp --disable-nls --disable-shared --disable-threads --disable-tls --enable-checking=release --enable-languages=c,c++,fortran --enable-mingw-wildcard --with-gmp=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/libs --with-newlib --with-pkgversion='xPack GNU Arm Embedded GCC x86_64' --with-gnu-as --with-gnu-ld --with-system-zlib --with-sysroot=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/arm-none-eabi --with-native-system-header-dir=/include --disable-libatomic --enable-multilib --with-multilib-list=aprofile,rmprofile
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.3.1 20220712 (xPack GNU Arm Embedded GCC x86_64) 
COLLECT_GCC_OPTIONS='-mcpu=cortex-m3' '-mthumb' '-O0' '-fmessage-length=0' '-fsigned-char' '-ffunction-sections' '-fdata-sections' '-g3' '-I' 'E:\_ARM_workspace2\minimal\src' '-I' 'E:\_ARM_workspace2\minimal\inc' '-save-temps' '-v' '-MMD' '-MP' '-MF' 'src/main.d' '-MT' 'src/main.o' '-c' '-o' 'src/main.o' '-mfloat-abi=soft' '-mlibarch=armv7-m' '-march=armv7-m' '-dumpdir' 'src/'
 c:/program files/eclipse/toolchains/arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/11.3.1/cc1.exe -E -lang-asm -quiet -v -I E:\_ARM_workspace2\minimal\src -I E:\_ARM_workspace2\minimal\inc -imultilib thumb/v7-m/nofp -iprefix c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/ -isysroot c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi -MMD src/main.d -MF src/main.d -MP -MT src/main.o -dD -D__USES_INITFINI__ ../src/main.S -mcpu=cortex-m3 -mthumb -mfloat-abi=soft -mlibarch=armv7-m -march=armv7-m -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -fworking-directory -O0 -fpch-preprocess -fno-directives-only -o src/main.s
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/include"
ignoring nonexistent directory "c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/lib/gcc/arm-none-eabi/11.3.1/../../../../include"
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/include-fixed"
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/include"
ignoring duplicate directory "c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi/include"
#include "..." search starts here:
#include <...> search starts here:
 E:\_ARM_workspace2\minimal\src
 E:\_ARM_workspace2\minimal\inc
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/include
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/include-fixed
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/include
End of search list.
COLLECT_GCC_OPTIONS='-mcpu=cortex-m3' '-mthumb' '-O0' '-fmessage-length=0' '-fsigned-char' '-ffunction-sections' '-fdata-sections' '-g3' '-I' 'E:\_ARM_workspace2\minimal\src' '-I' 'E:\_ARM_workspace2\minimal\inc' '-save-temps' '-v' '-MMD' '-MP' '-MF' 'src/main.d' '-MT' 'src/main.o' '-c' '-o' 'src/main.o' '-mfloat-abi=soft' '-mlibarch=armv7-m' '-march=armv7-m' '-dumpdir' 'src/'
 c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/bin/as.exe --gdwarf-5 -v -I E:\_ARM_workspace2\minimal\src -I E:\_ARM_workspace2\minimal\inc -march=armv7-m -mfloat-abi=soft -meabi=5 -adhlns=src/main.o.lst -o src/main.o src/main.s
GNU assembler version 2.38 (arm-none-eabi) using BFD version (xPack GNU Arm Embedded GCC x86_64) 2.38.20220708
COMPILER_PATH=c:/program files/eclipse/toolchains/arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/11.3.1/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../libexec/gcc/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/bin/
LIBRARY_PATH=c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7-m/nofp/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../arm-none-eabi/lib/thumb/v7-m/nofp/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/;c:/program files/eclipse/toolchains/arm-none-eabi/bin/../arm-none-eabi/lib/
COLLECT_GCC_OPTIONS='-mcpu=cortex-m3' '-mthumb' '-O0' '-fmessage-length=0' '-fsigned-char' '-ffunction-sections' '-fdata-sections' '-g3' '-I' 'E:\_ARM_workspace2\minimal\src' '-I' 'E:\_ARM_workspace2\minimal\inc' '-save-temps' '-v' '-MMD' '-MP' '-MF' 'src/main.d' '-MT' 'src/main.o' '-c' '-o' 'src/main.o' '-mfloat-abi=soft' '-mlibarch=armv7-m' '-march=armv7-m' '-dumpdir' 'src/main.'
Finished building: ../src/main.S
 
Building file: ../src/procedures.S
Invoking: GNU Arm Cross Assembler
arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections  -g3 -x assembler-with-cpp -I"E:\_ARM_workspace2\minimal\src" -I"E:\_ARM_workspace2\minimal\inc" -Wa,-adhlns="src/procedures.o.lst" --save-temps -v -MMD -MP -MF"src/procedures.d" -MT"src/procedures.o" -c -o "src/procedures.o" "../src/procedures.S"
Using built-in specs.
COLLECT_AS_OPTIONS='-adhlns=src/procedures.o.lst'
COLLECT_GCC=arm-none-eabi-gcc
Target: arm-none-eabi
Configured with: /Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/sources/gcc/configure --prefix=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc --prefix=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc --infodir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/info --mandir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/man --htmldir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/html --pdfdir=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/share/doc/pdf --build=x86_64-pc-linux-gnu --host=x86_64-w64-mingw32 --target=arm-none-eabi --disable-libgomp --disable-libmudflap --disable-libquadmath --disable-libsanitizer --disable-libssp --disable-nls --disable-shared --disable-threads --disable-tls --enable-checking=release --enable-languages=c,c++,fortran --enable-mingw-wildcard --with-gmp=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/libs --with-newlib --with-pkgversion='xPack GNU Arm Embedded GCC x86_64' --with-gnu-as --with-gnu-ld --with-system-zlib --with-sysroot=/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/arm-none-eabi --with-native-system-header-dir=/include --disable-libatomic --enable-multilib --with-multilib-list=aprofile,rmprofile
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.3.1 20220712 (xPack GNU Arm Embedded GCC x86_64) 
COLLECT_GCC_OPTIONS='-mcpu=cortex-m3' '-mthumb' '-O0' '-fmessage-length=0' '-fsigned-char' '-ffunction-sections' '-fdata-sections' '-g3' '-I' 'E:\_ARM_workspace2\minimal\src' '-I' 'E:\_ARM_workspace2\minimal\inc' '-save-temps' '-v' '-MMD' '-MP' '-MF' 'src/procedures.d' '-MT' 'src/procedures.o' '-c' '-o' 'src/procedures.o' '-mfloat-abi=soft' '-mlibarch=armv7-m' '-march=armv7-m' '-dumpdir' 'src/'
 c:/program files/eclipse/toolchains/arm-none-eabi/bin/../libexec/gcc/arm-none-eabi/11.3.1/cc1.exe -E -lang-asm -quiet -v -I E:\_ARM_workspace2\minimal\src -I E:\_ARM_workspace2\minimal\inc -imultilib thumb/v7-m/nofp -iprefix c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/ -isysroot c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi -MMD src/procedures.d -MF src/procedures.d -MP -MT src/procedures.o -dD -D__USES_INITFINI__ ../src/procedures.S -mcpu=cortex-m3 -mthumb -mfloat-abi=soft -mlibarch=armv7-m -march=armv7-m -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -fworking-directory -O0 -fpch-preprocess -fno-directives-only -o src/procedures.s
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/include"
ignoring nonexistent directory "c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi/Host/home/ilg/Work/arm-none-eabi-gcc-11.3.1-1.1/win32-x64/install/arm-none-eabi-gcc/lib/gcc/arm-none-eabi/11.3.1/../../../../include"
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/include-fixed"
ignoring duplicate directory "c:/program files/eclipse/toolchains/arm-none-eabi/lib/gcc/../../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/include"
ignoring duplicate directory "c:\program files\eclipse\toolchains\arm-none-eabi\bin\../arm-none-eabi/include"
#include "..." search starts here:
#include <...> search starts here:
 E:\_ARM_workspace2\minimal\src
 E:\_ARM_workspace2\minimal\inc
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/include
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/include-fixed
 c:\program files\eclipse\toolchains\arm-none-eabi\bin\../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/include
End of search list.
COLLECT_GCC_OPTIONS='-mcpu=cortex-m3' '-mthumb' '-O0' '-fmessage-length=0' '-fsigned-char' '-ffunction-sections' '-fdata-sections' '-g3' '-I' 'E:\_ARM_workspace2\minimal\src' '-I' 'E:\_ARM_workspace2\minimal\inc' '-save-temps' '-v' '-MMD' '-MP' '-MF' 'src/procedures.d' '-MT' 'src/procedures.o' '-c' '-o' 'src/procedures.o' '-mfloat-abi=soft' '-mlibarch=armv7-m' '-march=armv7-m' '-dumpdir' 'src/'
 c:/program files/eclipse/toolchains/arm-none-eabi/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/bin/as.exe --gdwarf-5 -v -I E:\_ARM_workspace2\minimal\src -I E:\_ARM_workspace2\minimal\inc -march=armv7-m -mfloat-abi=soft -meabi=5 -adhlns=src/procedures.o.lst -o src/procedures.o src/procedures.s
GNU assembler version 2.38 (arm-none-eabi) using BFD version (xPack GNU Arm Embedded GCC x86_64) 2.38.20220708
../src/procedures.S: Assembler messages:
../src/procedures.S:17: Error: syntax error -- `ldr r2,=~(RCC_CFGR_HPRE_mask|RCC_CFGR_PPRE1_mask|RCC_CFGR_PPRE2_mask|RCC_CFGR_ADCPRE_mask|RCC_CFGR_MCO_mask)'
../src/procedures.S:20: Error: syntax error -- `ldr r2,=~RCC_CR_CSSON_mask'
make: *** [src/subdir.mk:26: src/procedures.o] Error 1
"make all" terminated with exit code 2. Build might be incomplete.

11:43:02 Build Failed. 3 errors, 0 warnings. (took 354ms)
jozi
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    Seems to work here (2.33.1) , what version of GNU assembler are you using? – Jester Oct 05 '22 at 15:21
  • This could be an assembler bug. As a workaround, can you e.g. do `foo=~(BIT_30 | BIT_27 | BIT_25 | BIT_5)` and then `ldr r0, =foo`? – fuz Oct 05 '22 at 16:58
  • @old_timer: `gcc -c foo.s` just runs the GNU assembler on it, on a normal install of the GNU toolchain, doesn't it? The question originally just said GCC; I added the mention of GAS because it's an assembler question about the GNU toolchain, not a compiler question. – Peter Cordes Oct 06 '22 at 01:58
  • gcc is in the title – old_timer Oct 06 '22 at 02:28
  • I had a typo, 2.35.2 and 2.39 work. gcc 12.2.0 also works. Not going to build any other versions. OP needs to add more info – old_timer Oct 06 '22 at 02:32
  • Works for me with `arm-none-eabi-as` version 2.39, and on Godbolt with Binutils 2.35.1 (https://godbolt.org/z/cP3GETfcz). This question needs a [mcve] with exact version numbers. Or maybe it was just a typo. Voting to close as missing a MCVE, especially since it's been 13 hours with no response from the OP, despite Jester's comment 15 minutes after it was posted. – Peter Cordes Oct 06 '22 at 04:37
  • @Jester: I'm using Eclipse IDE for Embedded C/C++ Developers version 2021-03 (4.19.0) and xPack GNU Arm Embedded GCC release 11.3.1-1.1. – jozi Oct 06 '22 at 06:04
  • @fuz: I have tried also your idea. `foo = ~(RCC_CFGR_HPRE_mask | RCC_CFGR_PPRE1_mask | RCC_CFGR_PPRE2_mask | RCC_CFGR_ADCPRE_mask | RCC_CFGR_MCO_mask)` produced ` ../src/procedures.S:113: Error: invalid operands (*UND* and *UND* sections) for `|' ../src/procedures.S:113: Error: invalid operands (*ABS* and *UND* sections) for `|' ../src/procedures.S:113: Error: invalid operands (*ABS* and *UND* sections) for `|' ../src/procedures.S:113: Error: invalid operands (*ABS* and *UND* sections) for `|'` – jozi Oct 06 '22 at 06:05
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    @jozi Are the symbols defined at this point? This looks like they are not. It might be easier if you could post a [mcve] of what you tried. – fuz Oct 06 '22 at 08:33
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    Why is your [mcve] gigantic? Mine (in the Godbolt link) was 3 lines, for two `.equ` directives and one `ldr`. Your code could obviously be cut down a ton and still reproduce the error. It doesn't have to be a program that does anything useful. But as fuz said, maybe you forgot to `.include` a file with the `.equ` directives. GAS trying to use symbol relocations is often due to external symbols not constants. Or perhaps constants defined later in the file than where you use them? Often that does work anyway, but in some cases the ambiguity between address vs. integer can make a difference – Peter Cordes Oct 06 '22 at 09:56
  • gcc is not a cross assembler it is a cross compiler – old_timer Oct 06 '22 at 10:14

1 Answers1

1

This is what a minimal example looks like.

.equ BIT_30, (1 << 30)
.equ BIT_27, (1 << 27)
.equ BIT_25, (1 << 25)
.equ BIT_5,  (1 << 5 )
ldr r0, = ~(BIT_30 | BIT_27 | BIT_25 | BIT_5)

That is implied from the info provided in the question. You did not indicate architecture so...

arm-none-eabi-as --version
GNU assembler (GNU Binutils) 2.39
Copyright (C) 2022 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `arm-none-eabi'.

arm-none-eabi-as so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   e51f0004    ldr r0, [pc, #-4]   ; 4 <BIT_5-0x1c>
   4:   b5ffffdf    .word   0xb5ffffdf

No errors nor warnings.

arm-none-eabi-gcc -c so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   e51f0004    ldr r0, [pc, #-4]   ; 4 <BIT_5-0x1c>
   4:   b5ffffdf    .word   0xb5ffffdf

cp so.s so.S

arm-none-eabi-gcc -c so.S -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   e51f0004    ldr r0, [pc, #-4]   ; 4 <BIT_5-0x1c>
   4:   b5ffffdf    .word   0xb5ffffdf

and now

arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c so.S -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   4800        ldr r0, [pc, #0]    ; (4 <BIT_5-0x1c>)
   2:   0000        .short  0x0000
   4:   b5ffffdf    .word   0xb5ffffdf

getting closer to your code

so.inc

.equ BIT_30, (1 << 30)
.equ BIT_27, (1 << 27)
.equ BIT_25, (1 << 25)
.equ BIT_5,  (1 << 5 )

so.s

.include "so.inc"

ldr r0, = ~(BIT_30 | BIT_27 | BIT_25 | BIT_5)

still works

arm-none-eabi-as -mcpu=cortex-m3 so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   4800        ldr r0, [pc, #0]    ; (4 <BIT_5-0x1c>)
   2:   0000        .short  0x0000
   4:   b5ffffdf    .word   0xb5ffffdf

GNU assembler version 2.38 (arm-none-eabi) using BFD version (xPack GNU Arm Embedded GCC x86_64) 2.38.20220708 ../src/procedures.S: Assembler messages: ../src/procedures.S:17: Error: syntax error -- ldr r2,=~RCC_CFGR_HPRE_mask|RCC_CFGR_PPRE1_mask|RCC_CFGR_PPRE2_mask|RCC_CFGR_ADCPRE_mask|RCC_CFGR_MCO_mask)' ../src/procedures.S:20: Error: syntax error -- ldr r2,=~RCC_CR_CSSON_mask'

So if we look at procedures.S we can easily provide a minimal example of the problem:

so.s

ldr r0, = ~(BIT_30 | BIT_27 | BIT_25 | BIT_5)

gives

arm-none-eabi-as -mcpu=cortex-m3 so.s -o so.o
so.s: Assembler messages:
so.s:2: Error: syntax error -- `ldr r0,=~(BIT_30|BIT_27|BIT_25|BIT_5)'

There we go. reproduced.

You include this red herring though

But GNU toolchain refuses to evaluate the constant expression producing Syntax error. (I can use only ldr r0, =BIT_30 for example).

so.s

ldr r0, =BIT_30

arm-none-eabi-as -mcpu=cortex-m3 so.s -o so.o
arm-none-eabi-objdump -d so.o

so.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <.text>:
   0:   4800        ldr r0, [pc, #0]    ; (4 <.text+0x4>)
   2:   0000        .short  0x0000
   4:   00000000    .word   0x00000000

arm-none-eabi-ld so.o -o so.elf
arm-none-eabi-ld: warning: cannot find entry symbol _start; defaulting to 0000000000008000
arm-none-eabi-ld: so.o:(.text+0x4): undefined reference to `BIT_30'

As expected.

provide the definition

.equ BIT_30, (1 << 30)
ldr r0, =BIT_30

and

arm-none-eabi-as -mcpu=cortex-m3 so.s -o so.o
arm-none-eabi-ld so.o -o so.elf
arm-none-eabi-ld: warning: cannot find entry symbol _start; defaulting to 0000000000008000
arm-none-eabi-objdump -d so.elf

so.elf:     file format elf32-littlearm


Disassembly of section .text:

00008000 <__bss_end__-0x10004>:
    8000:   f04f 4080   mov.w   r0, #1073741824 ; 0x40000000

As expected.

Had you tried this instead

so.s

ldr r0, =~BIT_30

You would have seen the problem

arm-none-eabi-as -mcpu=cortex-m3 so.s -o so.o
so.s: Assembler messages:
so.s:2: Error: syntax error -- `ldr r0,=~BIT_30'

Just like you see in procedures.S and actual minimal examples above.

old_timer
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