Is there a way to stop a simulation after a set amount of time?

Question

Say I want a testbench simulation to run for 5000ns. Is there a way to tell the testbench to do this?

I'm aware I can edit simulation runtime in Vivado, but I want a way to do this in code.

Answer 1

The common way to stop a simulation after a fixed amount of time is to use $finish in an initial block in the source code:

initial #5000ns $finish;

Refer to IEEE Std 1800-2017, section 20.2 Simulation control system tasks, for further details.

See also ChipVerify