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Where does RIP gets its next instruction? Is there a pre ordered list of memory addresses in the compiled exe that is loaded at start or OS/processor calculate them according to the top down structure of op-codes of compiled assembly at runtime. I mean whether that code should be loaded into contiguous memory region so RIP gets it by continuously incrementing or decrementing current or first instruction memory address and if so how processor/OS know instruction length in order to identify one instruction from another, I mean if there is some convention like setting a bit flag.

Duke William
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  • The next instruction to be executed is the instruction following the current one, unless the current instruction is a jump instruction or some sort of interrupt or exception occurs. There is list of memory addresses or similar data structure as you envision it. – fuz Jul 09 '22 at 01:10
  • typo: there is **no** list of instruction-start addresses. x86 machine code is a byte stream that's not self-synchronizing: you need to know a valid start point to decode from. – Peter Cordes Jul 09 '22 at 02:47
  • @PeterCodes So CPU instructions sets should be designed there is no conflicts of validation? ( Like if there are 89febb48, d2f5c2, ebb48d2 and f5c2, there can be no 89fe, so there are no two concurrent valid possible instructions, right? (in at least x86-64) – Duke William Jul 09 '22 at 06:28
  • @Duke WIlliam Instructions need to be uniquely prefix-recognizable for the CPU to read them. But there is no requirement that a valid instruction can be inside the byte sequence of a larger instruction or even overlap the boundary between two instructions. Most obvious case is that if there is an instruction encoded as 0xAB 0xCD, then the instruction move eax,0x12CDAB34 will contain that instruction as part of the 0x12CDAB34 value . The hardware design requirement is only that the CPU can decode instructions in a correct forward sequence . – jb_dk Jun 22 '23 at 04:28

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