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In the J. Sorin book "Primer on Memory Consistency and Cache Coherence" I found the next paragaph about RMW optimistion in the SC model:

More aggressive implementations of RMWs leverage the insight that SC requires only the appearance of a total order of all requests. Thus, an atomic RMW can be implemented by first having a core obtain the block in state M in its cache, if the block is not already there in that state. The core then needs to only load and store the block in its cache—without any coherence messages or bus locking—as long as it waits to service any incoming coherence request for the block until after the store. This waiting does not risk deadlock because the store is guaranteed to complete.

Can somebody explain me, what this means? If we have two cores, first of them perform RMW to the A mem block, and the second perform Write request to the A block, what will happen?

jbapple
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ov3rdr1v337
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1 Answers1

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When a core wants to do a RMW operation, it acquires exclusive access to the cache line by invalidating it on all other cores. As soon as exclusive access is acquired, the cache line is 'locked' (so the CPU will not respond to cache coherence messages of other cores for that cache line).

This way the RMW is guaranteed to be atomic because no other core can steal the cache line between the read and write of that cache line.

If another other core wants to write to that cache line, it needs to wait till the owning core has completed the read+write to that cache line.

pveentjer
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