(a) What are the dimensions of the logical memory, of the logical address and of a page?
Possibly the most plausible assumptions are that the size of a logical address space is 256 MB and that there are 1024 logical pages per logical address space. This means:
page size = logical address space size / logical pages per logical address
page size = 256 MiB / 1024
page size = 256 KiB
The number of bits in a logical address can be determined from the logical address space size:
logical address size = log2(logical address space size) bits
logical address size = log2(256 MiB) bits
logical address size = 28 bits
For 2 levels of page tables; a logical address must be split into 3 pieces: an index into the 1st level page table, an index into the 2nd level page table, and an offset within the page. From the page size we can determine:
offset into page = log2(page size) bits
offset into page = log2(256 KiB) bits
offset into page = 18 bits
We also know that the size of a logical address must equal the sum of the sizes of its 3 pieces, or:
logical address size = 1st page table index size + 2nd page table index size + offset into page
28 = 1st page table index size + 2nd page table index size + 18
10 = 1st page table index size + 2nd page table index size
Now we start getting into trouble again. In theory (and in practice for some CPUs) it's possible for the 1st level page table size to be different to the 2nd level page table size.
Let's make another assumption. If 1st level page table is the same size as the 2nd level page table, and both indexes must add up to 10 bits, then it's not unreasonable to assume that the both indexes are 5 bits each.
If a page table index is 5 bits, then a page table must have 2**5 = 32 (or 1 << 5 = 32) entries.
We know that the size of a page table is:
page table size = entries per page table * size of page table entry
..but because we don't know the size of a page table or the size of a page table entry; we don't have enough information to determine anything else about the page table.
Note that often the size of a page table is the same as the page size (which would be 256 KiB), and in that case we could do "size of page table entry = page table size / entries per page table = 256 KiB / 32 = 8192 bytes". However; typically the size of a page table entry is related to the size of a physical address (e.g. 32 bits or 4 bytes, or 64 bits or 8 bytes); and 8192 bytes per page table entry is extremely implausible. This would imply that one or more assumptions is wrong (e.g. maybe the assumption that page table size and page size are equal).
(b) What are the dimensions of the physical memory, the physical address and a frame?
It's "overwhelmingly likely" that the physical page size is equal to the logical page size (which is 256 KiB).
There's isn't any information that can tell use anything else about the dimensions of physical memory. For example, if we could assume that the size of a physical address is the same as the size of a page table we could determine the size of the physical address space; but we don't know anything about the size of a page table entry so we can't even make possibly false assumptions.
(c) Considering a memory access time equal to 100ns (specific memory time without consider the overhead due to paging), an access time to the TLB equal to 10ns with parameter α equal to 95%, what the page fault time must be in order for the decrease in performance due to the page fault management is less than 10% with a hit rate of 98%?
I can't make sense of this question. Typically page faults have nothing to do with TLB hits and TLB misses, and occur when:
software crashed (e.g. SIGSEGV signal when you use an uninitialized pointer to attempt to access memory that doesn't exist)
the OS has to fetch data from secondary storage (from swap space, from a file)
the OS has to copy data (e.g. a page was set to "copy on write", possibly due to a previous fork(), and the page was written to)
