My goal is to display something on a VGA display with the resolution of 640x480px. I really want to stick with this resolution for other reasons, but we will see.
The problem:
Some lines appear dimmer and some appear lighter, also there is a large black border on the left side. I'm pretty sure that this is not (purely) due to my "bad signal timing" though.
(Please ignore the white scratch)
My setup:
- Altera Cyclone IV FPGA
- 3x330 Ohm resistors (on R,G,B lines) (and I'm driving the VSYNC and HSYNC directly with 3V3)
- Monitor NEC MultiSync EA232WMi (manual)
Verilog code:
module vga_test (
output wire HSYNC,
output wire VSYNC,
output wire enable,
output wire r,
output wire g,
output wire b,
// 50 MHz at clk
input wire clk
);
reg [32:0] hor_counter;
reg [32:0] ver_counter;
reg [32:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
if (enable == 1) begin
if (hor_counter[2:0] == 3) begin
g <= 1;
end else begin
g <= 0;
end
end
// Vertical counter
if (hor_counter == 1271) begin
enable <= 0;
end if (hor_counter == 1303) begin
HSYNC <= 0;
end if (hor_counter == 1494) begin
HSYNC <= 1;
end
hor_counter <= hor_counter + 1;
if (hor_counter == 1589) begin
// if (hor_counter == 800) begin
hor_counter <= 0;
ver_counter <= ver_counter + 1;
g <= 0;
if (ver_counter <= 480) begin
enable <= 1; end
end
// Horizontal counter
if (ver_counter == 490) begin
VSYNC <= 0;
end if (ver_counter == 492) begin
VSYNC <= 1;
end
if (ver_counter == 525) begin
ver_counter <= 0;
end
end
endmodule
What is very interesting, is that the monitor did not pick this up as 640x480, but as 720x480. This would maybe solve the why there is the black border, but the user manual says that 640x480 is supported. And this is not just with this monitor, I tried some other I have on hand with similar results. Maybe there is something with the signal timing that I'm not getting? I would't be surprised if the "picture" looked stretched, similar to this post, but this looks like a sinusoidal pattern.
