How can I set a SSE floating point exception by instruction and tigger the execution of this floating point trap at the same time if this exception isn't masked ?
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Peter Cordes
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Bonita Montero
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You mean without actually running an instruction like `mulps` with NaN inputs? You want to what, `stmxcsr [rsp-4]` / something / `ldmxcsr [rsp-4]` and then trigger any now-unmasked exceptions that were already raised, but not trigger any new ones? I don't know of a way to simulate an FP exception (the OS / IDT can distinguish `int 13h` vs. an actual `mulss`), but if you don't care which FP exception, you could maybe load MXCSR and turn `mxcsr & mask != 0` into a 0.0 or NaN float so mulss raises an invalid exception or not. But underflow/overflow/subnormal/precision are all maybe separate. – Peter Cordes Jun 01 '22 at 16:55
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I've developes a fast trunc() algorithm with MSVC in assembly (about four times faster, and the same speed like natively with libstdc++). I want to trigger an invalid opcode exception that might be catched with Windows' structured exception handling if this exception is unmasked. I don't want to have some substitute code that does this by manual 0.0 / 0.0 division because the debugger of a programmer that uses this code might stop there and this could be confusing in a trunc()-function. I don't know if MSVC's trunc only sets the invalid flag or actually "also" triggers an catchable exception. – Bonita Montero Jun 01 '22 at 17:19
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Wait what, #UD invalid opcode (illegal instruction)? Your question says you want to trigger a floating-point exception. – Peter Cordes Jun 01 '22 at 17:22
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Also, your last comment makes it sound like you don't want to modify MXCSR, instead that you want FP truncation to raise an exception if any are applicable, in case your function gets called with something unmasked. That's very different from trying to trap after unmasking an exception where the sticky bit for it recorded that one had already happened in the past. You should update your question to clarify your goals here. – Peter Cordes Jun 01 '22 at 17:25