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I am being asked to create a data segment using the .byte and .word directives to store values the values 0x01, 0x02, 0x03, 0x04 as bytes and the value 0x12345678 as a word. My code would be:

.data
    b1: .byte 0x01
    b2: .byte 0x02
    b3: .byte 0x03
    b4: .byte 0x04
    w1: .word 0x12345678

Then I want to use the lbu,lhu and lw to load into $t0,$t1,$t2 the values: 0x01, 0x0201 and 0x12345678 respectively.

What I am doing for that is:

    lbu $t0,b1  #this works
    lhu $t1,0(b2)   #this doesn't work, gets an error
    lw $t2,w1   #also works

My error is exception and unaligned address in inst/data fetch: 0x10010001. How do I load more than 1 byte as a halfword? Is my declaration of variables in the data segment wrong? Do I maybe want smth like:

byte_array: .byte 0x01,0x02

Thank you all for the help.

Erik Eidt
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user1512676872
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  • Fun fact: if you were using a MIPS32r6 CPU, that would run without faulting. That rework of the ISA added a requirement that unaligned loads work (possibly slowly, possibly even via trapping to an assist from helper code). https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64 - that allowed removing LWL / LWR (unaligned load word left/right parts) – Peter Cordes Apr 23 '22 at 13:05

1 Answers1

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You're attempting to load a half word (lhu) that is declared as a .byte.  That is a size mismatch, which goes to the error you're getting.

But the processor doesn't care about the size mismatch, but rather the alignment.  So, if you want to load a half word (two bytes) they must start on an even byte boundary, which isn't the case for your data set up.

lhu $t0, b1 will work, as will lhu $t0,b3, and lhu $t0,w1 as well because these data are at even addresses.  However, b2 and b4 are at odd addresses.

A C compiler would not let you perform the size mismatched loads in the first place, without some serious casting, which would get you back to these unaligned errors on MIPS.  Further, an x86 processor would allow the misaligned access, though in some cases those would be slower than the aligned equivalents.

Because misaligned accesses require more hardware and also that compilers can generally avoid these problems using their type systems to prevent them, some designs choose to forgo the extra hardware and MIPS is one of them.

You can also alter the alignment by inserting padding — one extra byte inserted between b1 & b2 would change b2's alignment allowing to load b2 and b3 using lhu.  Because w1 is declare as a .word the assembler knows it needs to be word aligned, so inserting that one byte between b1 & b3 will cause w1 to require 3 bytes of additional alignment padding (which the assembler will provide due to the .word data declaration being used).

When you use this kind of size mismatch, there will also be the issue of endianness.  The MIPS simulators will use the same endianness as the underlying processor so you'll generally see little endian behavior when loading 2 bytes.  If you declare two .bytes instead of using one .half you will have to pick a byte order.

Erik Eidt
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  • Re: the weird behaviour of classic MIPS assemblers (like MARS) inserting padding *before* the `w1:` label because of what they see after it (a `.word` directive): See [MARS MIPS simulator's built-in assembler aligns more than requested?](https://stackoverflow.com/a/59926496) for details / comparison with normal modern assemblers like GAS. – Peter Cordes Apr 23 '22 at 12:59
  • MARS is written in Java and always simulates a little-endian MIPS regardless of the ISA it's running on. SPIM works as you describe, simulating a MIPS with the same endianness as the host CPU. (It's written in C) – Peter Cordes Apr 23 '22 at 13:22
  • Thank you I understood the theory but i still cannot grasp how I would go about solving my question. How would I load 2 bytes as a halfword even if I were to align? And how would I align in the first place? – user1512676872 Apr 23 '22 at 13:30
  • The following directives accomplish alignment: `.half`, `.word,` `.float`, `.double`, and finally, `.align`. – Erik Eidt Apr 23 '22 at 17:29