Noob question. I want to compile bar.c with object file foo.o to an executable bar. I have this in a Makefile:
bar: foo.o
cc bar.c foo.o -o bar
I run $ make -n and get :
cc -c -o foo.o foo.c
cc bar.c foo.o -o bar
I'm looking at the first line of output cc -c -o foo.o foo.c. I didn't write an explicit rule compiling foo.c to foo.o. Does make do this implicitly when it sees a .o target?
Yes, GNU make has a catalog of built-in rules:
Compiling C programs
n.o is made automatically from n.c with a recipe of the form ‘$(CC) $(CPPFLAGS) $(CFLAGS) -c’.
Linking a single object file
n is made automatically from n.o by running the linker (usually called ld) via the C compiler. The precise recipe used is ‘$(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)’.
so you could just write:
bar: bar.o foo.o
