I am currently trying to program my PortentaH7 using the registers in the STM32H747 datasheet. So far I was only trying to access one core (M7) and now I want to try using the two cores at the same time. There are a lot of exemples on how to use both at the same time but none explains where the CORE_CM7 and CORE_CM4 are defined. Here is what I have done up till now :
volatile uint32_t* const SYSCFG_UR1 = (uint32_t *) 0x58002704;
volatile uint32_t* const RCC_GCR = (uint32_t *) 0x58024400A0;//to boot M4
void boot_CM4(void){
*SYSCFG_UR1 = (1<<0);//BCM4 = 1;
*RCC_GCR|=(1<<3);//BOOT_C2
}
This function should boot the M4 core. Most of the codes I have read online use :
#ifdef CORE_CMx
#endif
And it allows them to work with the CORE_CMx. My question is how is CORE_CMx defined. The datasheet here : https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf has me thinking that I should use the SYSCFG_UR3 register to write the starting address of the core in order to define CORE_CMx. However there is close to no information on this register in the datasheet. Any hints is appreciated.