working of `line compiler directive in system verilog

Question

Can someone please explain the working of `line compiler directive in system verilog tried to read it's working from LRM but was not able to understand it

Answer 1

The `line directive works the same as it does in other languages like C (What does #line mean?).

The main use is for tools that generate SystemVerilog code from another language so that any messages generated by the resulting SystemVerilog code can point back to the original code, instead of the translated code. This even works for tools that expand SystemVerilog macros, and makes for a good example. Suppose I have this 5 line file top.sv

module top;
`include "defines.h"
   `M(A)
   `M(B)
  initial x.x=0; // elaboration error
endmodule

And this 5 line file defines.h

int i1;
`define M(arg) \
   int L1_``arg; \
   int L2_``arg;
int i2;

The output from an SystemVerilog macro preprocessor is this 26 line file out.sv

`begin_keywords "1800-2017"

`line 1 "top.sv" 0
module top;
  
`line 1 "defines.h" 1
int i1;
  


`line 4 "defines.h" 0

int i2;

`line 6 "defines.h" 0

`line 2 "top.sv" 2

        int L1_A;     int L2_A;
        int L1_B;     int L2_B;
  initial x.x=0;
endmodule
   

`end_keywords

If I try to compile and run this out.sv file, the error gets reported on line 5 of top.v, not line 22 of out.sv .