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I tried to compile the following with NASM

shl di

which, according to this very non-sketchy source should multiply di by 2 once. However, I get an "invalid combination of opcode and operands" from NASM. After a bit of head-scratching, resolved to using

shl di, 1

which is magically OK with NASM and everything is OK with me too, except that now I am left with a question because, off the top of my head, I could have sworn that the first form was a thing, but maybe I'm misremembering things.

So, which is it?

Jester
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Morpheu5
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    Depends on assembler. Apparently nasm requires the count even if it's 1. It will nevertheless emit the machine code for the implicit version. – Jester Mar 23 '22 at 21:24
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    The implicit-count form (in the asm source) is a thing in GAS. For example in AT&T syntax: [SAR command in X86 assembly with one parameter](https://stackoverflow.com/q/12813962) is the opposite question from this, people puzzled by the one-operand form. (GAS does still assemble `shr $1, %di` into the implicit-count form, not an immediate count of 1). As @old_timer loves to say, assembly language (source text) depends on the tool, not just the machine code / ISA. – Peter Cordes Mar 23 '22 at 22:39
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    Anyway, as always you should look at how your assembler (NASM) assembles them to machine code. It's the same bytes, so there's literally zero difference in what the CPU executes. – Peter Cordes Mar 23 '22 at 22:55
  • I had noticed that the bytes produced were those I expected, hence the confusion. Thanks of clarifying. – Morpheu5 Mar 25 '22 at 06:08
  • Near duplicate: [SAR command in X86 assembly with one parameter](https://stackoverflow.com/q/12813962) - took me a while to find, had to google `site:stackoverflow.com x86 shift implicit count` – Peter Cordes Jun 28 '22 at 10:47

1 Answers1

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Apparently, NASM requires the count even if it's 1. Inspection of the generated machine code reveals that shl di and shl di, 1 indeed generate the same opcodes.

Morpheu5
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