-2

Hello,

I'm making a project where I want to bit-bang the JTAG protocol. According to the AN4666 provided by ST, DMA + GPIO can achieve high speeds in bit-banging synchronous protocols.

I want to:

  1. Generate N PWM pulses (the CLK signal).
  2. With the falling edge of each pulses, I want to set some GPIO with DMA.
  3. With the rising edge, I want to read from the GPIO using DMA.

What is the best way to achieve these specs using HAL?

Samer Sadek
  • 1
  • 1
  • You need to make some effort yourself before people will help you. No one is going to do your whole project for you. – Tom V Mar 19 '22 at 11:40

1 Answers1

0

even withtout dma you can reach quite high freq bit banged i/o i'll say in range 2 - 10MHz assuming fast enougth mcu and gpio bus clock high enough (48 96MHz) Clock just wan't be as stable and may suffer "stall" say idle time when iterrupt occur vs dma. but is way simpler

for DMA base , if you use 3 bit of one port, one for clk and one for TDI and one for TDO then use 2 dma one to wr and one that rd on same timer source (if possible) at double rate of the TCK signal the data in is rebuilt by taking teh i bit of one read data over 2 index like 0 2 4 or 1 3 5 ... depending on edge you want and how you wr clk array in mem is coded.

last if your jtag chain is 8 bit multiple SPI is even simpler and dma easy ;)

Michel Sanches
  • 428
  • 3
  • 9