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I am new to VHDL and writing program for receiving the serial data, which is dependent on 2 clocks and one RESET signal. One is FPGA's main source clock and another one is the external SPI master clock.

The written is like below:

    process(reset, main_clk, ext_clk)               
    begin
        if(reset = '0') then
        rx_data <= x"0000";
            elsif(chip_sel = '0') then
                if(ext_clk'event and ext_clk = '1') then    
--              rx_data <= rx_data;
                    if(main_clk'event and main_clk = '1') then
                    --- receiving data serially

But Xilinx tool is giving error:

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks.

How to overcome this error?

James Z
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hardware_engineer_blr
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  • See [ask]. You've abstracted your problem to the extent what you're trying to do is unclear. There are no complete VHDL statements nor declarations in your question. It appears you're trying to describe a serial shift register whose output is parallel loading into a register on a separate clock, yet the error message is saying you've named the parallel bus between them the same as the output register (rx_data). In general two different clocks shouldn't be evaluated in the same if or conditional signal assignment statement. Draw it out, is it something like a 74HC595? – user16145658 Jan 23 '22 at 07:36
  • this code is for (Slave FPGA) receiving the 16-bit serial data from external SPI master (USB-SPI : MCP2210). Here I pasted the lines of initial receiving. So SPI master 's Serial clock and Slave FPGA's main clock are to be in sync right ? – hardware_engineer_blr Jan 23 '22 at 09:56
  • It comes down to : learn digital hardware design as a separate topic from the language itself. Then you can use the language as a means of expressing that design. And a good basic rule is: use one clock for the entire design where you possibly can (as well as enable signals where you want to select some but not all clock edges) –  Jan 23 '22 at 16:56

1 Answers1

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It's because you use 'event on ext_clk and main_clk which the tools use to infer clocks. Your design should only be sensitive to main_clk and reset. De

Ryan Tennill
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