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I'm currently trying to understand booting process of AM65x SoC by Texas Instrument and I'm getting confused on SPL. Can somebody please correct me if I'm wrong? Here is what I understanding so far. (Assume we are using TMDX654IDKEVM.)

SPL is second piece of SW that is running, and according readme in u-boot should run on R5 cores. In TI terminology it get called tiboot.bin and it is produced by u-boot config am65x_evm_r5_defconfig, isn't it? And it is not only binary file straight from compiler, but it have some header with load address added, isn't it?

Next task for this component is to load sysfw (from TI) into M3 core and setup DRAM controller. That is somehow clear to me, except one thing, I'm still not sure where is code from DRAM config in u-boot.

Then we have working DRAM and we can load big things, so we are loading full u-boot with all features that is able to load kernel and rootfs from various sources. Am I correct if I say that this second u-boot binary is get from u-boot config am65x_evm_a53_defconfig? If so, what is A53 SPL in above readme link? Is there two u-boot binaries running on A53 core?

Many thanks in advance.

Vladislav
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Yes, on the A53 (and for other TI SoCs in this overall family, ie the whole J72 line) we load an SPL on the Cortex-A core and that loads the full U-Boot on the Cortex-A.

Tom Rini
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