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guys. How cortex pipeline is working during step by step debugging? I can see registers and memory are changing every single step when using debugger. Does debugger commands to flush pipeline every single step to synch its mem,reg,peri status? or emulate fetched opcode's expected outcome? Sometimes I encoutered async exception due to instruction fetched a few step before. <= It gives me confusion when debugging.. Any comments would be appreciated

Thanks

GONGDOL
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  • Interesting question. I can tell you that async exception I've seen are always linked to bus error. Bus access are asynchronous, processor keep going till data is needed and wait state are added. – Damiano Jan 14 '22 at 14:19

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