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I'm currently attempting to solve the following homework question:

Assume that one 16-bit and two 8-bit microprocessors are to be interfaced to a system bus. The following details are given: 8pts All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-​driven I/O, and DMA. All microprocessors have a 16-bit address bus. Two memory boards, each of 64-Kbytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and: Give the system bus specifications in terms of number and types of lines.

We didn't actually cover this content in class, so I'm a bit lost. My first instinct is to use 3 interrupt lines to address the 6 combinations of peripherals and memory boards (ceil(log2(6)) = 3 lines needed), and use interrupt-driven I/O for requests. Is this a viable option?

Additionally, is it possible to address the full 64kb * 2 = 128kb shared memory? Since the processors can only support 16-bit address lines, one would assume that the max size of the address space is 2^16 = 64kb, but that's only half of the total memory space. Is it possible to address all 128kb, and, if so, how?

Thanks in advance.

Charles Buchanan
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  • It sounds like a classic "write down what's in the teacher's mind" question rather than "write down what makes a sound system design". Parallel buses and external memories are very outdated technology. They seem to want you to invent some crazy flagging interrupt scheme where different MCU waves flags at each other before accessing memory. However, it would be sufficient just to have a chip select line per memory board, then poll it before access. If busy, wait, otherwise claim it. In the real world, nobody would design such a horrible bad system, they'd use MCU on-chip flash. – Lundin Dec 20 '21 at 07:25
  • It is in any event a hardware design issue rather then a software development issue and belongs at https://electronics.stackexchange.com/. Also it is not clear what the memory will be used for , if it is to be memory-mapped data/executable, then ideally you'd have a system that was transparent to the software so each device could access the memory as it it had it all to itself - especially if that were the only memory available to the processor. Details such as "one DMA line" are not helpful without specifying the purpose and behaviour of such a "line" - what the part data sheet is for. – Clifford Dec 20 '21 at 12:26
  • @Lundin You say that we should use software polling with an interrupt line per memory board. However, how would we determine to which MCU an interrupt is directed? – Charles Buchanan Dec 20 '21 at 13:10
  • @CharlesBuchanan I don't see why you need to use interrupts at all. First to grab the chip select line, first to serve. It really sounds as if they are describing an early 1990s ISA bus PC or something. Nobody designs systems like that any longer, because they were crap. – Lundin Dec 20 '21 at 13:27
  • I’m voting to close this question because it is not a programming problem – Dalija Prasnikar Jan 03 '22 at 11:34

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