I want to know how do i can find the length of a string in verilog.
Example: CAT is a 3 letter string and APPLE is letter string. How do i create a code of this in verilog?
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1Please provide enough code so others can better understand or reproduce the problem. – Community Dec 10 '21 at 11:12
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There are no 'strings' in Verilog at all. Verilog only operates on bits. There is some syntactic sugar which allows assigning codes of ascii letters to an array of bits. As such, there are no tools to operate on strings as in 'c'. Every symbol in the string literal is mapped to sequential 8 bits in the vector.
In order to find a meaningful length of the string you need to create a rule for it and follow the rule while creating strings. For example you can follow a 'c' notation and use '0' as a terminating character. Then you will need to scan the array of bits for it and calculate length.
Another example is to keep its length as a separate variable.
Depending on your needs, you can switch to SystemVerilog and use 'string' type as a non-synthesizable construct but which provides you with the string related tools in test bench.
