How can I resolve RISC-V assembly pseudo instructions to true RISC-V instructions?

Question

I need to build large RISC-V assembly programs (.a/.as/.S files) using a specific toolchain that doesn't support pseudo-instructions. (Synopsys' ASIP designer tool creates a custom assembler for a customized CPU / instruction set.)

The programs assemble fine with GCC (which uses GAS), but the assembler that I need to use does not recognize pseudo-instructions. It only works on programs written only using actual RISC-V machine instructions.

Is there a tool or a GCC or GAS option that I can use to resolve all the pseudo instructions to true RISC-V instructions, without changing the rest of the program?

You mean assembler, not compiler, right? You're not actually compiling *to* asm with GCC, you're just using `gcc` to invoke `as` and `ld`, I think, for `.S` files that are already hand-written. (You might be able to assemble and then disassemble, but most ways of doing that lose labels and directives.) — Peter Cordes, Nov 29 '21 at 11:46
It might be easiest to improve this custom assembler to support the standard pseudo-instructions documented in the RISC-V manuals. Or if this assembler has a macro language, to define them as macros. I think you could probably do that with GAS `.macro` for most / all pseudo-instructions, but you're not using GAS. — Peter Cordes, Nov 29 '21 at 11:49
Just curiously -- which tool are you using? Does this apply to all pseudo instructions or just some? Is there any difference between official pseudo instructions and GCC-specific ones? — Lindydancer, Nov 29 '21 at 13:53
You can write a sed/awk/other script, or write your own preprocessing tool. — Erik Eidt, Nov 29 '21 at 14:33
@PeterCordes Yes you are right, strictly speaking, I am starting at the assembler and skipping compilation. I can't really modify this custom assembler, since it is not one specific one. This is meant to work for all automatically-generated compilers that Synopsys' ASIP designer tool creates based on custom processor designs (Hence why these compilers only recognize the true instruction set). I could always write a script to do the task, but the whole point of this question is finding out if this already exists, potentially saving time and implementation errors. — Sherif AbdelFadil, Nov 30 '21 at 13:25

score 2 · Answer 1 · answered Nov 29 '21 at 17:38

I am not sure I completely understand your question. But I think that maybe a combination of using a script and objdump or just manually swapping sections of your code may work.

Let's say we have a test.S file with the following content (those are all pseudo-instructions):

start:
    nop
    li a2, 42
    mv a3, a4
    not a5, a6
    neg a7, a0
    beqz t0, 1f
    negw t1, t2
    sext.w t4, t5
    seqz t6, a0
    snez a1, a2
    sltz a3, a4
    sgtz a5, a6
1:
    ret

Using gcc we can compile it into an object using this command: gcc -c test.S -o test.

Now, using the objdump tool we can print the instructions of the object: objdump -d test.

test:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <.L1^B1-0x2c>:
   0:   0001                    nop
   2:   02a00613                li      a2,42
   6:   86ba                    mv      a3,a4
   8:   fff84793                not     a5,a6
   c:   40a008b3                neg     a7,a0
  10:   00028e63                beqz    t0,2c <.L1^B1>
  14:   4070033b                negw    t1,t2
  18:   000f0e9b                sext.w  t4,t5
  1c:   00153f93                seqz    t6,a0
  20:   00c035b3                snez    a1,a2
  24:   000726b3                sltz    a3,a4
  28:   010027b3                sgtz    a5,a6

000000000000002c <.L1^B1>:
  2c:   8082                    ret

objdump prints the content using pseudo-instructions. However, you can use the -M flag to make objdump not to use pseudo-instructions: objdump -d -M no-aliases test.

The result is this:

test:     file format elf64-littleriscv


Disassembly of section .text:

0000000000000000 <.L1^B1-0x2c>:
   0:   0001                    c.addi  zero,0
   2:   02a00613                addi    a2,zero,42
   6:   86ba                    c.mv    a3,a4
   8:   fff84793                xori    a5,a6,-1
   c:   40a008b3                sub     a7,zero,a0
  10:   00028e63                beq     t0,zero,2c <.L1^B1>
  14:   4070033b                subw    t1,zero,t2
  18:   000f0e9b                addiw   t4,t5,0
  1c:   00153f93                sltiu   t6,a0,1
  20:   00c035b3                sltu    a1,zero,a2
  24:   000726b3                slt     a3,a4,zero
  28:   010027b3                slt     a5,zero,a6

000000000000002c <.L1^B1>:
  2c:   8082                    c.jr    ra

You can extract all the instructions from your object files with this.

How can I resolve RISC-V assembly pseudo instructions to true RISC-V instructions?

1 Answers1