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I was learning about loops in Verilog and wanted to create a simple clock with time period of 20ns. I am getting the error below whenever I am trying to run the code in EDA Playground.

module Pulse(clock);
  output reg clock;
  
  initial
    begin
      clock = 1'b0;
    end
  
  forever #10 clock = ~clock;      //Error is here
endmodule

design.sv:9: syntax error design.sv:9: error: invalid module item.

Circuit_Breaker0.7
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2 Answers2

3

forever is a procedural statement; it does not create a process like initial or always . You can put the forever inside the initial block` or just write

 always #10 clk = ! clk;
dave_59
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2

forever cannot be used outside of a procedural block. It will work if you put it the initial block:

initial
   begin
      clock = 1'b0;
      forever #10 clock = ~clock;  
   end
Serge
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