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My professor said:

Usually, L1 cache is included in L2 cache, but that's not correct for L2 and L3

But why? This doesn't make sense to me... we are just using extra expensive space for nothing useful (we can use it for something else)

Peter Cordes
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Algo
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    L1d and L1i are physically separate from L2. Do you mean the *data in them* is also included in L2 cache? Some CPUs do use an inclusive L2, some use an inclusive L3 (like Intel since Nehalem, until recent server chips). But Intel CPUs use a NINE cache policy for L2 wrt. L1i/d, so often the same data is included in both, but after some evictions can diverge. (Especially on Skylake-client where L2 is only 4-way associative.) [Which cache mapping technique is used in intel core i7 processor?](https://stackoverflow.com/a/49099990) – Peter Cordes Nov 08 '21 at 23:21
  • Some CPUs, notably AMD, have even used Exclusive L2 or L3 caches. See https://en.wikipedia.org/wiki/Cache_inclusion_policy. NINE is basically the "default", where the outer cache doesn't make any special effort to cooperate with an inner cache to maintain inclusion or exclusion. There are advantages either way for quick write+back eviction vs. caching more total stuff vs. letting the outer inclusive cache answer MESI coherency requests / act as a snoop filter. – Peter Cordes Nov 08 '21 at 23:25

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