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I have very basic doubt ,how PCIE Root complex moves DMA transaction from PCIe endpoint to Host memory. Suppose ,Pcie EP(End Point) want to initiate a DMA write transaction to HOST memory from its local memory. So DMA read channel present on PcieEP ,will read data from its local memory,then PCIe module in the PcieEP convert this to Pci TLP transaction and direct it to PCIE root complex. So my Query is

  1. Know how PCIE rootcomplex ,will come to know that it has to redirect this packet to HOST Memory ?
  2. How is the hardware connection from PCIeroot complex to Host Memory ? Will there be DMA Write in PCIe root complex to write this data to Host Memory .
SUN
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  • 1. PCIE write transactions are routed by address. The root complex looks up the address in the TLP and determines that it is the address of a memory location. The root complex must have some sort of lookup table to determine this. 2. The mechanism that the root complex uses to send the data to memory is highly implementation specific. – prl Oct 31 '21 at 08:28
  • Thanks for your reply. For 1 : I understand how for a Non-DMA transaction RC(Root Complex) routes the packet downstream by checking its base and limit register to see if packet belongs to any Device(Switch/EP) below it.However for upstream DMA packet which reaches to RC , I couldn't find any specific info how this routing is done to System Memory. Any pointer will be of great help. Similarly for 2 also if you can point any specific stuff. – SUN Nov 05 '21 at 17:11

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The PCIe RC will receive the TLP and it will have a address translation function which optionally translates the address and send the packet to its user side interface. And usually after the PCIe RC, there is IOMMU logic which converts PCIe address to host physical address (and checks permissions). The IOMMU has for PCIe uses address translation table on memory for for each {bus, device, function} pairs or even PSID(process space id) and then that packet will have new physical address and go to an interconnect (usually supporting cache coherency). The interconnect receives the packet from iommu (the iommu becomes a master to the interconnect), and that interface node has system memory map having information where the addressed target is located within the interconnect. The system address map should be set by the firmware before OS runs. (usually there is interrupt controller - Interrupt translation service for arm system - after iommu and before the interconnect to intercept MSI-message signaled interrupt- and generate interrupt to the main interrupt controller).

Tomerikoo
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Chan Kim
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