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I'm trying to do good logic in Makefile for my project. Let's assume i have a Makefile with rules:

...
NAME := prog_name
...
all: subsystem

subsystem:
    @$(MAKE) -sC $(D_LIB)
    @$(MAKE) -s $(NAME)

$(D_OBJ):
    @mkdir -p $(D_OBJ)

$(NAME): $(D_OBJ) $(OBJ) $(H) $(LIB)
    $(CC) ...  -o $(NAME)

$(D_OBJ)%.o: $(D_SRC)%.c $(H) $(LIB)
    @$(CC) ... -c $< -o $@

.PHONY: all subsystem

When i run command:

make (make all)

It check $(D_LIB) for any changes, then run make for $(NAME) rule. And if there were changes in the library or program files my program recompiles.

But if i run command:

make prog_name

It would not run subsystem rule and i will not know about the changes in the library in any way. Accordingly, the program won't be rebuilt. So I am tormented by the question of how to make it interconnected. If i run command make (all) or run command make prog_name, i should check every dependies for my programm and re-build it if necessary.

vsezanatodazheeto
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    It is very difficult to infer your intention from a makefile that doesn't work. If `prog_name` depends on `$(D_LIB)`, then why is "$(D_LIB)" not a prerequisite of "$(NAME)"? – Beta Oct 29 '21 at 02:35
  • Note: `$(D_OBJ)` is apparently a directory. Using directories as regular prerequisites (like you do in the rule for target `$(NAME)`) is a bad idea because their last modification time changes each time a file is added or deleted or renamed in the directory. You probably use this to guarantee that the `$(D_OBJ)` directory exists before the recipe for `$(NAME)` is executed (and I do not understand why). If this is your goal, declare it as an [order-only prerequisite](https://www.gnu.org/software/make/manual/make.html#Prerequisite-Types). – Renaud Pacalet Oct 29 '21 at 07:13
  • in case you are doing it for not learning purpose and need practical result, consider using https://github.com/cppfw/prorab it has this and many more problems solved and allows writing simple clean and universal `makefile`s – igagis Oct 29 '21 at 15:02

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