24 Hour Clock code, getting fan out error

Question

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss); 

    wire [4:0] enable;
    
    assign enable[0] = ss[3:0] == 4'd9;
    assign enable[1] = ss[7:0] == 8'h59;
    assign enable[2] = {mm[3:0],ss[7:0]} == 12'h959;
    assign enable[3] = {mm[7:0],ss[7:0]} == 16'h5959;
    assign enable[4] = {hh[3:0],mm[7:0],ss[7:0]} == 20'h95959;

    bcd in1(clk, reset, ena, ss[3:0]);
    bcd in2(clk, reset, enable[0], ss[7:4]);
    bcd in3(clk, reset, enable[1], mm[3:0]);
    bcd in4(clk, reset, enable[2], mm[7:4]);
    bcd in5(clk, reset, enable[3], hh[3:0]);
    bcd in6(clk, reset, enable[4], hh[7:4]);
        
    always @ (*) begin
       if(reset) begin
           pm <= 0;
           hh <= 8'h12;
           ss <= 8'h00;
           mm <= 8'h00;
       end
        else if(ena) begin         
            
         // ss <= ss == 8'h59;
         // mm <= (mm == 8'h59 & ss == 8'h59) ?? 8'h00 : mm;
         // hh <= (hh == 8'h12 & mm == 8'h59 & ss == 8'h59) ?? 8'h01 : hh;
            
        end
    end
   
endmodule

module bcd(input clk, reset, ena,
           output [3:0] q);
    
    always @ (posedge clk) begin
        q <= reset ? 0 : (ena ? (q == 4'd9 ? 0 : q + 1) : q);
    end
        
endmodule

I'm trying to understand why when I try to run this code, I'm getting this error:

Error (12014): Net "hh[7]", which fans out to "hh[7]", cannot be assigned more than one value File: /home/h/work/hdlbits.2188345/top_module.v Line: 28
    Error (12015): Net is fed by "GND"
    Error (12015): Net is fed by "bcd:in6|q[3]" File: /home/h/work/hdlbits.2188345/top_module.v Line: 49

I'm getting that for all of the other elements in ss, mm and hh, one by one. I'm not seeing how I'm trying to give it a value in more than one place. Very confusing.

toolic · Answer 1 · 2021-10-14T22:54:45.540

The error message tells you that you are assigning to hh[7] in 2 places. The 1st line is:

bcd in6(clk, reset, enable[4], hh[7:4]);

and the 2nd line is:

       hh <= 8'h12;

In the 1st line, hh is driven by the q output signal of the bcd module.

One way to fix the problem is to delete the always block from top_module. The only thing that code does is set the signals during reset, which is already done in the bcd module.

Here is modified code that compiles without errors for me:

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    wire [4:0] enable;
    
    assign enable[0] = ss[3:0] == 4'd9;
    assign enable[1] = ss[7:0] == 8'h59;
    assign enable[2] = {mm[3:0],ss[7:0]} == 12'h959;
    assign enable[3] = {mm[7:0],ss[7:0]} == 16'h5959;
    assign enable[4] = {hh[3:0],mm[7:0],ss[7:0]} == 20'h95959;

    bcd in1(clk, reset, ena, ss[3:0]);
    bcd in2(clk, reset, enable[0], ss[7:4]);
    bcd in3(clk, reset, enable[1], mm[3:0]);
    bcd in4(clk, reset, enable[2], mm[7:4]);
    bcd in5(clk, reset, enable[3], hh[3:0]);
    bcd in6(clk, reset, enable[4], hh[7:4]);
endmodule

module bcd(input clk, reset, ena,
           output reg [3:0] q);
    
    always @ (posedge clk) begin
        q <= reset ? 0 : (ena ? (q == 4'd9 ? 0 : q + 1) : q);
    end
    
endmodule

Note also that I removed reg from the hh, mm and ss ports, and I added reg to the q port.

24 Hour Clock code, getting fan out error

1 Answers1