How do Verilog and VHDL handle conflicting assignments after (n+delta) cycles?

Question

To set the stage, assume a circuit that computes ((a AND b) or c), with the inputs a,b,c changing at the same time, e.g. taken from clocked registers. The delay of the AND gate is negligible, and therefore not modeled at all, but the delay of the OR gate is significant, say 5ns.

The gates are modeled by using an operator and a delayed assignment in two separate processes:

Verilog:
    (process 1) temp <= a & b;
    (process 2) out <= #5 temp | c;

VHDL:
    (process 1) temp <= a and b;
    (process 2) out <= temp or c after 5ns;

Now with the right old and new input values, a glitch occurs: (a = 1, b = 1, c = 0) -> (a = 0, b = 1, c = 1). This causes the temp value (output of the AND gate) to become 0 in a delta cycle, and therefore schedule a change of the OR gate to 0 after 5ns. Simultaneously, c becomes 1 and schedules a "change" of the OR gate to 1 (at that time it still is 1).

Now the fun part: Let the inputs change at time 0ns. The change of the OR gate to 1 is scheduled at time 0ns, for time 5ns. The change of the OR gate to 0 is scheduled at time (0ns + 1delta), for 5ns later. A "too simple" model would schedule both for time 5ns and risk that they get executed in the wrong order, leaving the output of the OR gate at 0 erroneously.

The question now is, how do Verilog and VHDL make sure that the glitch gets resolved correctly? Things they could do it that I can imagine:

allow scheduling for (N cycles + D delta cycles), so the change of the OR gate to 1 gets scheduled for (5ns + 1delta) and is guaranteed to be executed last.
schedule both for time (5ns), but have the action of scheduling an assignment remove all assignments for the same driver scheduled for the same time
schedule not just the assignment, but the whole computation for time (5ns) and delay the evaluation of gate inputs to that time. However, the answer to this question seems to imply that this is not what happens: Understanding the Verilog Stratified Event Queue

Please note that I am trying to understand the behaviour prescribed by the two languages, not achieve a specific outcome.

[How much research effort is expected of Stack Overflow users?](https://meta.stackoverflow.com/questions/261592/how-much-research-effort-is-expected-of-stack-overflow-users) For VHDL consider a simulation that can be reproduced by your readers and asking a specific question. The 3 things that you imagine aren't all completely clear. The third one appears invalid. See IEEE Std 1076-2008 IEEE Standard VHDL Language Reference Manual 10.5.2 Simple signal assignments through 10.5.2.2 Executing a simple assignment statement and 14.7 Execution of a model. *Projected Output Waveform* (a queue). — user16145658, Sep 19 '21 at 11:11
The `or` and `and` operators are found in value expressions of the VHDL simple signal assignments. — user16145658, Sep 19 '21 at 11:11
verilog code you provided makes no sense outside of a corresponging always block or an assign statement. Define 'glitch' in you case. Behavior of glitches will depend on your definition, your always block and the rest of the logic. Usually to resolve glitches in any language, flops are used. — Serge, Sep 19 '21 at 14:19

score 0 · Answer 1 · answered Sep 19 '21 at 17:33

For the signal assignments you have shown, Verilog and VHDL both guarantee last write wins. As other have commented, it would have helped to show the complete context of the statements to confirm that is what you intended.

There will be no glitch because the c transition from 0→1 happens before the temp transition from 1→0, separated by a delta cycle. Although you cannot determine the ordering between different concurrent processes, if there is a deterministic ordering within the same process, last write to the same variable wins.

How do Verilog and VHDL handle conflicting assignments after (n+delta) cycles?

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