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what is right way to make latch in verilog? When i try synthesizing both ways on vivado i get latch generated in both the cases.i am trying to understand do we use blocking statement or non-blocking statement?

i) always @(enable,input) begin q <= input; end

ii) always @(enable,input) begin q = input; end

PARUL
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2 Answers2

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Use blocking assignments.

For synthesis, only use non-blocking assignments for edge sensitive sequential logic.

dave_59
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  • Seems that Cummings in "Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!" recommends nonblocking for latches. Do you have a reason for suggesting using blocking assignments instead? – cic Jan 17 '23 at 23:04
  • @cic Unless you need to provide non-blocking delays, like `q<= #1 in;` non-blocking assignments have no benefit for latches. – dave_59 Jan 18 '23 at 04:03
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None of the ways you provided should be used to make latches.

Commonly used programming pattern looks like the following:

always @*
   if (en)
       q <= inp;
Serge
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