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What if I have a PCI bus (w/o PCI-PCI bridges) with 3 devices: spy-device, sender PCI device and receiver device (e.g. bridge from PCI to CPU).

The sender start transferring data to receiver. The transmitter state of spy-device is Z (disconnected from bus). Can the spy device listen to the bus and have all data sent from sender copied?

Update: I'm ready to buy special FPGA with PCI adaptor and program it.

osgx
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On legacy PCI (assuming no PCI-to-PCI bridges in between), it is possible to "listen" to bus transactions intended for other devices. We have some in-house developed debug hardware that does exactly this. You need to make sure that your listening devices does not "claim" the transaction itself, though. Most off-the-shelf PCI IP cores and ASICs will not be suitable for this task.

On PCI Express, it is not so easy due to the point to point nature of the bus. Your listening device would have to be physically between the peripheral device and the CPU.

myron-semack
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  • And if I consider verilog; the state of output pins will be Z and I will be able to listen to them as input? – osgx Aug 01 '12 at 21:15
  • Your "sooping" device should have all of its bus signal pins configured as inputs. Not sure what that means in Verilog. – myron-semack Aug 02 '12 at 12:36
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That depends. On PCI, I think all are connected in a shared bus. So probably yes. But on PCI-Express each device has its own "bus" - so they are not physically connected (directly).

benzaita
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  • Yes, PCI-Express is star of p2p links not a bus. But is it physically possible, when spy device put its pins in Z state (sometimes called [Hi-Z](http://en.wikipedia.org/wiki/Three-state_logic) or high impedance state) to read data from bus? – osgx Jun 08 '12 at 21:56