How to create an VHDL-2008 alias to a signal in an hierarchy created by for-generate?

Question

I have an hierarchy created by a for-generate like this:

INST: for ... generate
. . .
end generate;

It creates many instances, as expected, named as INST__0, INST__1, etc, which names have a double underscore on it.

When I try to create an alias to a signal A in this hierarchy I got an error like "Invalid literal" because the path to the signal has double underscores, which is indeed invalid in VHDL:

alias A is <<signal DUT.INST__0.COUNTER.A: std_logic>>;

Is there any way to solve this problem? Prevent for-generate using double underscores, maybe?

Thanks

In your instance of Counter, do A'path_name. Does that too have the double underscore in it? Have you looked at extended names. That may give you a way of allowing the double underscore. — Jim Lewis, Jul 23 '21 at 01:41
Reporting the `A'path_name` returned something different - `:tb:dut:inst(0):counter:a`, what makes much more sense. Using this path in the `alias` statement solved the problem. The path `dut.inst__0.counter.a` was just a misleading artifact of the waveform viewer. Good catch, tks! — Walter X, Jul 23 '21 at 02:41

score 1 · Answer 1 · answered Jul 23 '21 at 01:28

You do not provide a reproducible or complete example nor demonstrate the syntax location of your alias declaration. Particular note the lack of a the loop parameter which your attempt alludes to include values 0 and 1.

See IEEE Std 1076-2008 8.7 External names

pathname_element ::=
      entity_simple_name
    | component_instantiation_label
    | block_label
    | generate_statement_label [ ( static_expression ) ]
    | package_simple_name

and the accompanying semantic description of the the static expression:

b)Second, for each package simple name in a package pathname, or for each pathname element in an absolute or relative pathname, in order, the previously identified declarative region is replaced as the identified declarative region by one of the following:

...
5)For a generate statement label, the declarative region of the equivalent block corresponding to the generate statement. If the generate statement is a for generate statement, the pathname element shall include a static expression, the type of the expression shall be the same as the type of the generate parameter, and the value of the expression shall belong to the discrete range specified for the generate parameter. The type of the expression shall be determined by applying the rules of 12.5 to the expression considered as a complete context, using the rule that the type shall be discrete. If the type of the expression is universal_integer and the type of the generate parameter is an integer type, an implicit conversion of the expression to the type of the generate parameter is assumed.

We see that the static expression included in parentheses following the generate statement label is a value of the loop parameter.

A -2008 example that can be analyzed, elaborated and simulated:

entity for_gen_label is
end entity;

architecture fum of for_gen_label is

begin
INST:
    for i in 0 to 3 generate
COUNTER:
        block
            signal a: boolean;
        begin
PROC_LABEL:
            process
            begin
                report a'INSTANCE_NAME;
                wait;
            end process;
        end block;
    end generate;
end architecture;

where we also see that the -2008 predefined attribute 'INSTANCE_NAME can also demonstrate path name elements (GHDL):

for_gen_label.vhdl:16:17:@0ms:(report note): :for_gen_label(fum):inst(0):counter:a
for_gen_label.vhdl:16:17:@0ms:(report note): :for_gen_label(fum):inst(1):counter:a
for_gen_label.vhdl:16:17:@0ms:(report note): :for_gen_label(fum):inst(2):counter:a
for_gen_label.vhdl:16:17:@0ms:(report note): :for_gen_label(fum):inst(3):counter:a

The format of the 'INSTANCE_NAME predefined attribute value is given in 16.2.5 Predefined attributes of named entities.

The two underscores is a C(++) affectation for names which indicates you're probably getting information from the user interface of a simulator capable of supporting multiple hardware description languages. GHDL, a batch simulator supporting only VHDL produces output that adheres to VHDL path name elements:

ghdl -r for_gen_label --disp-signals-map
.for_gen_label(fum).inst(0).counter.a: 00007FBDBD504700 net: 0
.for_gen_label(fum).inst(1).counter.a: 00007FBDBD5047A0 net: 0
.for_gen_label(fum).inst(2).counter.a: 00007FBDBD504840 net: 0
.for_gen_label(fum).inst(3).counter.a: 00007FBDBD5048E0 net: 0
...

while incidentally demonstrating the entire path. VHDL unlike some other HDL's is not identifier case sensitive.

As your example demonstrated, the VHDL path in for-generated instances are `name(index)`, not `name__index`. I was misled by the hierarchy path used by the **waveform viewer** - it has been consistent for non-generated instances so I assumed it would be correct for generated ones. My bad. Tks — Walter X, Jul 23 '21 at 02:57

score 0 · Answer 2 · answered Jul 23 '21 at 01:43

0

I would try an extended identifier. I would try both of the following, but I suspect the first one will get you there (and the second one not):

alias A is <<signal DUT.\INST__0\.COUNTER.A : std_logic>>;

and

alias A is <<signal \DUT.INST__0.COUNTER.A\ : std_logic>>;

I am concerned though the second one would be seen as a single identifier.

answered Jul 23 '21 at 01:43

Jim Lewis

3,601
10
20

Interesting feature the extended identifiers, much alike Verilog. I tried both examples, they solved the literal error but the signal couldn't be found - no surprise, as I realized that the real VHDL path in generated block is `inst(0)` instealdof `inst__0`. See comment above. Tks – Walter X Jul 23 '21 at 02:54

How to create an VHDL-2008 alias to a signal in an hierarchy created by for-generate?

2 Answers2