Adding delay to each logic gate

Question

I'm learning and building some Verilog codes, but now what matters to me is understanding the delays in logic gates. I'm trying to code this simple combinational circuit with 5ns delay in each logic gate, but I don't exactly know if that's it:

`timescale 1ns/1ps

module comb_circuit(input wire A, B, C, D, output wire Z);
  wire E, F;

  assign #5 E = (A & B & C) | D;
  assign #5 F = (B ~| C) ~& A;

  assign #5 Z = E ^ ~F;

endmodule

In the code above, does every logic gate have 5ns delay or just the wires (E, F, Z)?

Serge · Accepted Answer · 2021-06-29T15:06:16.110

2

You have a behavioral verilog code with no structural gates in it. Therefore, the delays will work in a behavioral sense.

From standard:

A delay given to a continuous assignment shall specify the time duration between a right-hand operand value change and the assignment made to the left-hand side.

In your code there will be a 5 ns delay in evaluation of a lhs (E, F, Z) value. It will be delayed relative to the last change of the value of a right-hand-side expression.

Delays in always blocks behave differently.

It is a in simulation only behavior and it will not synthesize in hardware.

edited Jun 29 '21 at 15:06

answered Jun 29 '21 at 14:26

Serge

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Thanks for your help, my friend! So a delay in a logic gate would look like this right? "and #5(E, A, D)", with E being an output wire and A and D being an input wire. – Inovaula Jun 29 '21 at 21:00
yes, you need to specify each logical gate in a structural way. – Serge Jun 29 '21 at 21:06

score 2 · Answer 2 · answered Jun 29 '21 at 14:53

The delays are only on the wires E, F, and Z in the code you wrote. There are no logic gates in you description at this point because you have not synthesized to a hardware representation. These delays are only used in simulation and ignored by synthesis. The actual delays need to be recalculated based on the target technology used to implement your equations.

Adding delay to each logic gate

2 Answers2