Initialize and increment a genvar variable inside nested for loop of system verilog

Question

I'm trying to write a synthesizable code in .sv to meet my requirements, but got stuck at the very end without a solution;

I've an incoming wire which is 99 bit wide and 10 (MAX) deep
I need to feed this to a module and get its output which is 99 bit
the output needs to be assigned to an array (99 bit wide ) from 0 .. max

I can't paste the snippet, but this is what I've coded:

--

param MAX = 10;
param TOT_INST = 45 ;
wire [98:0] inwire [MAX-1:0] ;
wire [98:0] outwire [TOT_INST-1:0]

genvar x,y,z ;
generate
     for (x = 0, z=0; x<=MAX-1; x=x+1, z=z+1 )
       begin : gen1
         for (y = x + 1; y<=MAX-1; y=y+1)
           begin : gen2
             some_module mod_inst ( .in1(inwire[x]), .in2(inwire[y]), .y(outwire[z]) );
           end
       end
endgenerate

-- The expectation is to get outwire[0] to be an output of inwire[0] and inwire[1], outwire[1] to be a function of inwire[0], inwire[1] etc. So, it becomes necessary to increment the index of outwire.

I used another genvar z for this purpose (to increment from 0 to 44). But, it looks like the SV doesn't support multiple genvar variables to be incremented? im getting compilation error at the for loop itself.

Is there any way to achieve what i need? I really appreciate you taking time to go through this question. Any insight would be really helpful.

Thanks Jr.

The code you show looks like x and z increment the same. Why do you need both variables? What is `TOT_INST`? How it is used in the loop you want to write. It might help to show the generate loop manually unrolled to see exactly what you are epexcting. — dave_59, Jun 23 '21 at 05:53
In your description both, outwire[0] and outwire[1] shouhld be function of the *same* set of inwire[0], inwire[1]. Is it what you really want? — Serge, Jun 23 '21 at 10:45
Thanks for the reply. There is a typo in my question. i need to pick two — juniorinVerilog, Jun 23 '21 at 14:21

score 2 · Answer 1 · answered Jun 24 '21 at 16:17

I understand your intent. It seems you are trying to use comma expressions, but they wont work here.

Also, it seems that the genvar can only be assigned in the initialization and increment of the for loop, otherwise it would be easy to increment them on the innermost loop.

Since you must have unique drivers to the outwires, and the number of entries you declared (45) matches the number of instances you will create I assume you simply want them to be set incrementally.

What I would do is to calculate the number of iterations algebraically and create a local parameter. If you can't see how, review triangular numbers.

parameter MAX = 10;
// Generalizing your TOT_INST
parameter TOT_INST = MAX * (MAX - 1) / 2 ;
wire [98:0] inwire [MAX-1:0] ;
wire [98:0] outwire [TOT_INST-1:0];

genvar x,y;
generate
  for (x = 0; x <= MAX-1; x = x + 1 ) 
  begin : gen1
    for (y = x + 1; y<=MAX-1; y=y+1)
    begin : gen2
      localparam z = TOT_INST - ((MAX - x - 2) * (MAX - x - 1)) / 2 + y - MAX;
      initial begin
        $display("%d %d %d", x, y, z);
      end
    end
  end
endgenerate

The formula would be simpler if we used the x in the inner loop.

Initialize and increment a genvar variable inside nested for loop of system verilog

1 Answers1