What is the reset type of the reset signal of an always_latch .?

Question

I don't have much knowledge on system verilog and I have the following question.

As I know, if an edge of a reset signal has been triggered in the sensitivity list of an always block then the reset type of that reset signal is 'asynchronous' I need to know, what is the reset type of the reset signal of an always_latch?

module test (input in_1,in_2,rst,clk,sig, output reg out_1,out_2,out_3);
  always_latch
  begin
    if(~rst) // what is the reset type of this reset signal.?
      out_3 <= 0;
    else if(~sig)
      out_3 <= in_1;
  end
  wire x,x2;
  second uu(x, x2, rst, clk, sig, out_1);
endmodule

module second(input i_1,i_2,r,c,sig, output reg o_1);
  reg z,zz;
  always@(negedge c or negedge r)
  begin
    if(~r) // asynchronous reset type
      z <= 0;
    else
      z <= i_1;
  end
  always@(posedge c or negedge r)
  begin
    if(~r)  // asynchronous reset type
       zz <= 0;
    else
      zz <= i_1;
  end
endmodule

score 3 · Accepted Answer · answered Jun 15 '21 at 06:39

Both resets are asynchronous. You cannot have a synchronous reset in a latch because there is no clock. The always_latch construct in your example creates an implicit sensitivity list

always @(rst or sig or in_1)

The reason the always sensitivity list has a negedge r is to filter out the change on the rising edge of r. If you didn't have that filter, the rising edge of r would trigger the block and be treated the same as clock edge.

What is the reset type of the reset signal of an always_latch .?

1 Answers1