1

I have a MIPS code. There are 189 instructions and 55 of them are memory instructions. There are some values that are given,
Data cache miss rate = 20%
Miss penalty = 100 Clock Cycles.

And the question is to calculate total CC for code and average CPI for instruction? I know these two things but I couldn't figure out how can use miss rate and miss penalty in the formula. Shouldn't be there an instruction cache rate?

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
hasanaliozkan
  • 13
  • 4
  • 1
    I guess you're supposed to assume that data cache misses are the only possible stalls? So no `mult` or `div` instructions, I guess, and no I-cache misses. If it's MIPS I then the pipeline doesn't know how to stall for anything except cache misses (code cache or data cache), or for an `mflo` or `mfhi` when the result isn't ready yet. (Later 5-stage MIPS can stall if you use a load result in the next instruction, instead of having to use a NOP if you can't otherwise fill the load delay slot.) – Peter Cordes Jun 12 '21 at 18:55
  • 1
    Anyway, you can easily write code that will run with CPI worse than 1 without cache misses, but I think only by using instructions like `mult` / `mflo`. MIPS 1 doesn't have interlocks for the load delay, and 1 branch-delay slot fully hides branch latency, making branch prediction unnecessary. – Peter Cordes Jun 12 '21 at 18:57

0 Answers0