1

I'm trying to build an JK FF with Async low active clear and preset. However verilog is giving me " design.sv:24: syntax error I give up." It looks like I have an error somewhere but I can't find it. I would appreciate every help

This is my design code

    module JKFF(clk,J,K,Q,Qbar,Clear,Preset);
      input J,K,clk,Clear;
      output Q, Qbar;
      reg Q;
      assign Qbar= ~Q;
      
      always@(negedge clk or negedge Clear or negedge Preset )
        begin
          if(!Clear)
            Q<=1'b0;
          else if(!Preset)
            Q<=1'b1;
          else if(Clear==1&&Preset==1)
            if (K==0 && J==0)
            Q <= Q;
            if (K==1 && J==0)
            Q <= 0;
            if (K==0 && J==1)
            Q <= 1;
            else
            Q <= ~Q;
            
        end
    endmodule;

This is my TB code

    module JKFF_tb;
    
     // Inputs
    
     reg J;
     reg K;
    
     reg clk;
    
     reg Clear;
    
     // Outputs
    
     wire Q;
    
     wire Qbar;
    
     // Instantiate the Unit Under Test (UUT)
    
    JKFF uut (
    
      .Q(Q), 
    
      .Qbar(Qbar), 
    
      .J(J),
      .K(K),
    
       .clk(clk), 
    
      .Clear(Clear)
    
      );
      initial begin
      clk=0;
      Clear=1;
      Preset=1;
         forever #10 clk = ~clk; 
      end
    
     initial begin 
     J= 1; K= 0;
     #100; J= 0; K= 1; 
     #100; J= 0; K= 0; 
     #100; J= 1; K=1; 
    end 
      // Add stimulus here

    endmodule
shaedrich
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RottenMush
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1 Answers1

2
  1. You don't declare Preset in module JKFF input list.
  2. You typo semicolon ; after endmodule keyword.
  3. You don't have code inside begin and end after else if(Clear==1&&Preset==1)
  4. You don't have else if in J and K conditions.
  5. In module JKFF_tb you don't declare Preset reg and you assign value to it.
  6. You don't pass Preset to JKFF module instance named uut.
module JKFF(clk,J,K,Q,Qbar,Clear,Preset);
    input J,K,clk,Clear, Preset;
    output Q, Qbar;
    reg Q;
    assign Qbar= ~Q;

    always@(negedge clk or negedge Clear or negedge Preset )
    begin
        if(!Clear)
            Q<=1'b0;
        else if(!Preset)
            Q<=1'b1;
        else if(Clear==1&&Preset==1) begin
            if (K==0 && J==0)
                Q <= Q;
            else if (K==1 && J==0)
                Q <= 0;
            else if (K==0 && J==1)
                Q <= 1;
            else
                Q <= ~Q;
        end
    end

endmodule

module JKFF_tb;

 // Inputs

 reg J;
 reg K;
 reg Preset;

 reg clk;

 reg Clear;

 // Outputs

 wire Q;

 wire Qbar;

 // Instantiate the Unit Under Test (UUT)

JKFF uut (

  .Q(Q), 

  .Qbar(Qbar), 

  .J(J),
  .K(K),

   .clk(clk), 

  .Clear(Clear),
  .Preset(Preset)

  );
  initial begin
  clk=0;
  Clear=1;
  Preset=1;
     forever #10 clk = ~clk; 
  end

 initial begin 
 J= 1; K= 0;
 #100; J= 0; K= 1; 
 #100; J= 0; K= 0; 
 #100; J= 1; K=1; 
end 
  // Add stimulus here

endmodule
ToTamire
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