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I want to monitor and allocate LLC space usage using Intel RDT. I wrote a program which will cause 100% cache miss as I expect. My machine's LLC size is 30.25 MB, and cache line size is 64 bytes. So I access a matrix column by column like so:

int matrix[524288][16];     //4 byte * 524288 * 16 = 32M byte
void bad_access();

int main() {
    int i = 0;
    cout << sizeof(int) << endl;
    while (i < 5000) {
        bad_access();
        i++;
    }
    return 0;
}

void bad_access() {
    int sum = 0;
    for (int j = 0; j < 16; j++) {
        for (int i = 0; i < 524288; i++) {
            sum += matrix[i][j];
        }
    }
}

I assumed that the program above would use all LLC space, but when I checked it with Intel RDT, I found that it only used less than 16 MB. I wondered how that happened.

J.Xin
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  • Why did you edit back to "my machine's LLC size **are** 30.25 MB"? Do you have a multi-socket machine with more than one L3 cache? But probably that's just a grammar misunderstanding, since you made the same change to the cache line size. All your lines have the same size, and that one *size* (singular) **is** 64 bytes. Not "are", you'd only say that in a case like "my per-core private L2 caches are 1MiB each". Or "The cache sizess are 32k, 256k, and 30.25 MiB for L1, L2 and L3". – Peter Cordes Jun 10 '21 at 06:00
  • You could say "the cache lines *are* 64 bytes", because then you're talking about the group of all cache lines, not the singular "size" attribute they all share. (Anyway, this English lesson isn't relevant to your question, sorry I don't what Intel RDT is. Although I did wonder if it could be related to adaptive replacement in L3 cache, which Intel has been doing since IvyBridge to reduce pollution from code like this that touches a lot of memory. https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/) – Peter Cordes Jun 10 '21 at 06:03
  • Already edited, thanks a lot! @PeterCordes – J.Xin Jun 11 '21 at 02:29

0 Answers0