iverilog: Syntax error in assignment statement l-value

Question

Why do I get syntax errors in my Verilog code?

The code:

module RegFile (
    input clk,
    input [4:0] rs1,
    input [4:0] rs2,
    input [4:0] wr,
    input reg[31:0] wd,
    input RegWrite,
    output reg[31:0] rd1,
    output reg[31:0] rd2);

    reg [31:0] file[31:0];

    integer i;
    initial begin
        i=0;
        while(i<32)
        begin
            file[i]=32'b0;
            i=i+1;
    end

assign rd1=file[rs1];
assign rd2=file[rs2];

always @(posedge clk) begin
    if(RegWrite)
        file[wr]=wd;
end

always@(file[0])
file[0]=32'b0;
    
endmodule

Here are the errors:

regfile.v:25: syntax error
regfile.v:27: Syntax in assignment statement l-value.

toolic · Answer 1 · 2021-05-28T13:29:09.133

The "l-value" syntax error happens because you make continuous assignments (using the assign keyword) to signals you declared as reg. You should not use the reg keyword in this case. Change:

output reg[31:0] rd1,
output reg[31:0] rd2);

to:

output [31:0] rd1,
output [31:0] rd2);

I also get a compile error on the following line:

input reg[31:0] wd,

You should not use the reg keyword for an input port. Change it to:

input [31:0] wd,

Finally, you are missing the matching end keyword for the while begin:

initial begin
    i=0;
    while(i<32)
    begin
        file[i]=32'b0;
        i=i+1;
    end // <----- add this
end

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iverilog: Syntax error in assignment statement l-value

1 Answers1